Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2000-07-06
2002-03-12
Pascal, Robert (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S300000
Reexamination Certificate
active
06356154
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to the use of field effect transistors (FETs) as voltage-controlled resistors in gain control circuits, and in particular to the use of an FET-based voltage-controlled resistor in a continuously variable wide-band gain control circuit.
2. Description of Related Art
A voltage-controlled resistor has a resistance that can be adjusted by an input control signal. Normally we want the current conducted by a voltage-controlled resistor be a linear function of the voltage across its load terminals. Thus while we want its resistance to be function of the voltage of a control signal applied to its control terminals, we do not want its resistance to vary with the voltage across its load terminals. Field effect transistors, particularly those fabricated using an “interdigitated” geometry, have long been used as voltage-controlled resistors because they exhibit a linear relationship between drain current I
d
and drain-to-source voltage V
ds
over a limited range of drain-to-source voltage. Since the conductance of an FET's channel region is a function of the gate-to-source voltage, a control signal applied to the gate of an FET effectively controls the drain-to-source resistance.
In fabricating an interdigitated FET, a linear gate stripe is diffused into a linear channel stripe with identical parallel drain and source contacts on each edge of the channel stripe. Such FETs are highly symmetrical since the drain and the source are substantially identical. Thus such an FET has the same response characteristics regardless of the polarity of V
ds
and direction of flow of I
d
. This makes an interdigitated FET very useful as a voltage-controlled resistor in differential circuits where current flows in either direction; the drain current I
d
remains linear despite the polarity of V
ds
.
Thus such voltage-controlled FET resistors are commonly used in differential gain control circuits.
FIG. 1
illustrates a well-known prior art differential gain control circuit
10
employing an FET transistor J
1
as a voltage-controlled resistor. A differential input signal V
IN
is applied across the bases of two bipolar transistors Q
1
and Q
2
and a differential output signal appears across the collectors of transistors Q
1
and Q
2
. A pair of matching resistors R
1
and R
2
are connected in series across the collectors of transistors Q
1
and Q
2
and a bias voltage −V
BIAS
is applied to the node between the two resistors R
1
and R
2
. A resistor R
3
and the drain-source channel of the FET transistor J
1
link the emitters of transistors Q
1
and Q
2
. A pair of current sources I
BIAS1
and I
BIAS2
supply bias currents to the emitters of transistors Q
1
and Q
2
.
The gain G of control circuit
10
is determined as follows:
G=(R
1
+R
2
)/(R
3
∥Rx)
where Rx is the drain-to-source resistance of FET J
1
and the quantity (R
3
∥Rx) is the resistance of the parallel combination of R
3
and RX, the quantity (R
3
Rx)/(R
3
+Rx). The voltage of a control signal V
CONT
applied to the gate of FET J
1
controls the drain-to-source resistance Rx. By increasing the voltage of V
CONT
we decrease the drain-to-source resistance Rx, thereby increasing the gain of circuit
10
. To avoid signal distortion it is necessary for the impedance between the emitters of transistors Q
1
and Q
2
to be independent of the voltage across those emitters. That is why transistor J
1
is implemented as a FET, an in particular a symmetric FET.
Gain control circuit of
FIG. 1
has some significant limitations. First, the FET drain-to-source channel may have significant parasitic capacitance in parallel with the channel conductance, and the parasitic capacitance can cause signal distortion in output signal V
OUT
through over-peaking.
Another problem arises when the input signal V
IN
has a non-zero common mode voltage. The common mode voltage of the V
IN
differential input signal is the average voltage of its +V
IN
and −V
IN
ends. Once we set the gain of FET J
1
by adjusting the voltage of control signal V
CONT
, we don't want that gain to change. In particular, we don't want the gain to be a function of the polarity of drain-to-source voltage V
ds
. However when the common mode input signal voltage is non-zero, the gate-to-source voltage V
gs
will be modulated by V
IN
and the channel resistance Rx of FET J
1
will vary with every cycle of the V
IN
signal, thereby causing gain compression for one polarity of the input signal and gain expansion for the opposite polarity of the input signal. This asymmetry in response produces second order harmonic distortion in of the output signal V
OUT
. A similar second order harmonic distortion in the output signal occurs when gain control circuit
10
is driven by a single-ended signal.
A symmetric FET is generally suitable for only relatively low frequency operation; high frequency FETs are typically asymmetric, but are not used as voltage-controlled resistors in differential gain control circuits because their asymmetry creates substantial harmonic distortion. Thus when we want to provide a gain control circuit in a high frequency integrated circuit employing asymmetric FETs in other circuits, providing a symmetric FET for the gain control circuit becomes problematic.
What is needed is a voltage-controlled resistor for use in a differential gain control circuit that can be implemented using high frequency, asymmetric FETs without substantially distorting the output signal. It would also be beneficial if the gain control circuit could use such an FET-based voltage-control resistor in a manner that avoids second order distortion resulting from an input signal having a non-zero common mode voltage.
SUMMARY OF THE INVENTION
A gain control circuit in accordance with one aspect of the invention generates a differential output signal in response to a differential input signal with a gain controlled by an input control signal employs two asymmetric field effect transistors (FETs) as a linear, voltage-controlled resistor. The use of asymmetric FETs to implement a linear voltage-controlled resistor makes the gain control circuit of the present invention convenient to use in high-frequency integrated circuit applications employing asymmetrical FETs.
In accordance with a second aspect of the invention, the FETs are interconnected drain-to-source with the control signal being applied to their gates. This results in a combined channel current that is a substantially linear and symmetric function of the input control signal voltage applied to the FET's gates.
In accordance with a third aspect of the invention, the gain control circuit includes two bipolar transistors, with the differential input signal being applied across their bases and the differential output signal being developed across their collectors. A resistor links the emitters of the two transistors, current sources are applied to the emitters, and a pair of resistors links each collector to a source of bias voltage.
In accordance with a fourth aspect of the invention, in a first embodiment thereof, the FET-based voltage-controlled resistor is connected between the emitters of the two transistors.
In accordance with a fifth aspect of the invention, in a second embodiment thereof, the FET-based voltage-controlled resistor is connected between the collectors of the two bipolar transistors, thereby reducing output signal distortion due to any input signal common mode component.
In accordance with a sixth aspect of the invention, the gain control circuit drives an emitter-follower output stage. The inherent drain-to-source parasitic capacitance of the two FETs reduces over-peaking distortion in the output signal of emitter-follower stage when the FETs are connected between the collectors of the two bipolar transistors.
The concluding portion of this specification particularly points out and distinctly claims the subject matter of the present invention. However those skilled in the art w
Bedell Daniel J.
Credence Systems Corporation
Nguyen Khanh V.
Pascal Robert
Smith-Hill and Bedell
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