FET balun transformer

Details FET balun transformer FET balun transformer

2000-01-11

2001-06-26

Pascal, Robert (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including balanced to unbalanced circuits and vice versa

C330S306000, C330S165000, C330S253000

Reexamination Certificate

active

06252460

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to an FET balun transformer.
In recent years, the operating frequencies of communications devices have been further raised or broadened to transmit and receive data of even larger capacities. For these purposes, a balun transformer is needed to convert a single-ended signal into differential signals with a phase difference of 180 degrees. A passive balun transformer, which is a combination of coils, has been generally used for a radio frequency circuit. Currently, however, an FET balun transformer, which includes multiple field effect transistors (FETs), is often used to meet the demand of broadening the signal frequency range or integrating as many devices as possible on the same chip. As for a signal with a frequency exceeding 1 GHz, which belong to a microwave or quasi-microwave range, in particular, an FET balun transformer is regarded as effectively contributing to downsizing the device.
Furthermore, a high-performance balun transformer, which includes gallium arsenide (GaAs) Schottky gate field effect transistors (i.e., MESFETs) exhibiting excellent radio frequency characteristics and low distortion while consuming just a small amount of current, is also used widely.
Hereinafter, a known FET balun transformer will be described with reference to FIG.
6
.
FIG. 6
illustrates a prior art FET balun transformer. As shown in
FIG. 6
, the balun transformer includes first, second and third FETs
31
,
32
and
33
. The drains of the first and second FETs
31
and
32
are connected to a positive power supply
36
by way of load resistors
34
and
35
, respectively.
The gate of the first FET
31
is connected to an input terminal
37
, while the gate of the second FET
32
is grounded. The sources of the first and second FETs
31
and
32
are connected in common to the drain of the third FET
33
, which operates as constant current source. The source of the third FET
33
is connected to a negative power supply VSS of −1 V, for example, via a biasing resistor
38
, while the gate thereof is connected to the negative power supply VSS directly. The drains of the first and second FETs
31
and
32
are connected to first and second output terminals
39
and
40
, respectively.
The gate and source of the third FET
33
are both connected to the negative power supply VSS because of the following reasons. Since a MESFET uses a Schottky gate, the gate-source voltage should be negative. Accordingly, if the gate biases of the first and second FETs
31
and
32
are set at 0 V, then the gate and source of the third FET
33
should be less than 0 V.
Next, it will be described how the conventional FET balun transformer operates. A single-ended RF signal is received at the input terminal
37
. In response, the current flowing through the first FET
31
changes. However, since the gate of the second FET
32
is grounded and a constant current flows through the third FET
33
, the total amount of currents flowing through the load resistors
34
and
35
does not change but the drain potential of the third FET
33
changes.
Thus, so long as the single-ended signal received at the input terminal
37
is located in the linear region of the first FET
31
, the drain voltage of the third FET
33
is equal to the source voltage of the first FET
31
. As a result, signals with mutually inverted phases are output through the first and second output terminals
39
and
40
.
The conventional FET balun transformer, however, needs not only the positive power supply
36
for supplying a positive potential to the drains of the first and second FETs
31
and
32
, but also the negative power supply VSS to set the gate and source of the third FET
33
at a negative potential. A device with the negative power supply VSS is too complicated and too large to be applied to an IC.
SUMMARY OF THE INVENTION
An object of the present invention is providing an FET balun transformer using the positive power supply alone, thereby downsizing a device including the FET balun transformer.
To achieve this object, according to the present invention, a positive bias voltage is applied to the gate of the second FET, which is grounded in the prior art configuration, thereby allowing the third FET to have positive gate and source voltages.
An FET balun transformer according to the present invention is adapted to convert a single-ended signal received at an input terminal into differential signals and then output the differential signals through first and second output terminals, respectively. The transformer includes first, second and third FETs and an AC grounded capacitor. The drain of the first FET is connected to a positive power supply and to the first output terminal, while the gate thereof is connected to the input terminal. The drain of the second FET is connected to the positive power supply and to the second output terminal. One terminal of the AC grounded capacitor is connected to the gate of the second FET, while the other terminal thereof is grounded. The drain of the third FET is connected to the sources of the first and second FETs, while the gate thereof is grounded.
In one embodiment of the present invention, the FET balun transformer may further include a bias circuit for biasing the gates of the first and second FETs at a predetermined positive potential.
In this particular embodiment, the bias circuit preferably includes a voltage divider and first and second resistors. The voltage divider is made up of a pair of resistors that are connected in series to each other at a connection node for dividing a voltage supplied from the positive power supply. The first resistor is connected to the gate of the first FET and to the connection node. The second resistor is connected between the gate of the second FET and the AC grounded capacitor and to the connection node.
In an alternate embodiment, the FET balun transformer may further include a bias regulator for regulating at least one of bias voltages applied to the gates of the first and second FETs.
In this particular embodiment, the bias regulator preferably includes a resistor and a variable resistor. One terminal of the resistor is connected to the positive power supply and the other terminal thereof is connected to the gate of the first FET. One terminal of the variable resistor is connected to the gate of the first FET and the other terminal thereof is grounded.
In another embodiment, the FET balun transformer may further include a series-resonant circuit, which is disposed between the first and second output terminals and causes a series resonance at a frequency twice higher than that of the single-ended signal received at the input terminal.
In this particular embodiment, the series-resonant circuit preferably includes a resonant coil, a resonant capacitor and a resonant resistor that are connected in series to each other.
In still another embodiment, the AC grounded capacitor may include a capacitive insulating film of high dielectric-constant materials. The AC grounded capacitor and the first, second and third FETs may be integrated on the same substrate.
In the FET balun transformer according to the present invention, the AC grounded capacitor is connected to the gate of the second FET, and the gates of the first and second FETs are biased at a positive potential. Accordingly, the gate and source of the third FET do not have to be set at a negative potential and no negative power supply is needed anymore. As a result, the FET balun transformer can be of a smaller size.
Also, according to the present invention, even if there is a phase difference between the output signals at the first and second output terminals due to harmonic distortion or difference in characteristic of the first and second FET, the bias regulator can cancel such harmonic distortion or variation. As a result, the phase difference between the output signals can be minimized.
Moreover, according to the present invention, the series-resonant circuit can reduce the impedance between the first and second output terminals at a

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