Fet array for operation at different power levels

Details Fet array for operation at different power levels Fet array for operation at different power levels

1998-02-17

1999-09-28

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257659, 257660, H01L 23552, H01L 2348, H01L 2352

Patent

active

059593571

ABSTRACT:
A FET package including one or more FETs includes an arrangement of three metallization layers for the gate, drain, and source terminals thereof. The layers include a gate runner metallizaton layer that allows the FETs to be arranged in a parallel manner so as to reduce the overall total on-state resistance to an optimum value, while allowing the gate switching capacitance to be increased to an optimized value. The gate runner metallization layer is arranged to minimize the overlapping capacitance between the gate and source terminals and between the gate and drain terminals. Additional semiconductor devices may be incorporated into the FET package using additional terminals interconnected through the metallization layers, thus providing additional functions.

REFERENCES:
patent: 4783695 (1988-11-01), Eichelberger et al.
patent: 5384691 (1995-01-01), Neugebauer et al.
patent: 5455442 (1995-10-01), Neilson et al.
patent: 5696403 (1997-12-01), Rostoker et al.

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