Ferroelectric non-volatile logic elements

Details Ferroelectric non-volatile logic elements Ferroelectric non-volatile logic elements

2002-02-12

2003-11-18

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S218000

Reexamination Certificate

active

06650158

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates generally to logic elements such as SR flip-flops, JK flip-flops, D-type flip-flops, master-slave flip-flops, parallel and serial shift registers, and the like and, more particularly, to logic elements that are rendered non-volatile by the addition of ferroelectric capacitors and supporting circuitry.
Integrated circuits can be divided into analog functions and digital functions. Most digital functions can be implemented using the following elements: combinatorial logic, clocked registers and memory. Until recently, a clear distinction was made between volatile memories such as SRAM and DRAM and non-volatile memories such as ROM, EPROM, EEPROM and Flash EEPROM. Volatile memories offer high speed and high density, but they lose data when the power supply is removed. Non-volatile memories, on the other hand, keep their data when the power supply is removed and offer relatively high density, but write times and write endurance are limited.
Today, ferroelectric memories are commercially available that provide non-volatility while retaining write performance similar to that of volatile memories. So, as ferroelectric memory technology continues to advance, the gap between volatile and non-volatile memory will continue to shrink.
Another gap exists between clocked registers and memory. Fundamentally, clocked registers, such as the multiple-purpose registers used in microcontrollers and microprocessors, are low-density memories combined with combinatorial logic in such a way as to create the desired register function. Because of the relatively late development of non-volatile memory and its poor write speed performance relative to volatile memories, clocked registers have always been volatile and most often based on cross-coupled devices similar to an SRAM cell.
Conversely, floating-gate memories require high currents to program each bit, each bit takes a long time to program, and current sensing is used to determine the state of the cell. In the current logic system design paradigm, data requiring non-volatility must either be backed up by a battery or stored in a low-write-speed non-volatile memory and restored byte-by-byte on power-up.
What is desired, therefore, is a class of logic circuits that retain the functionality and operating characteristics found in present-day integrated circuit versions of these logic circuits, while introducing the further benefit of non-volatility.
SUMMARY OF THE INVENTION
According to the present invention, the following description details the methodology used to render logic elements non-volatile through the strategic addition of ferroelectric capacitors and supporting devices. In each case, the building blocks of a cross-coupled sense amplifier are identified within the logic element and the basic cell is modified and/or optimized for sensing performance. More so than the fundamental logic elements involved, memory sense amplifiers require carefully balanced layout to properly detect the memory state over the lifetime of the part. Because of this, care is taken to create symmetry within the design that is easily translated into device layout.
The recent availability of high performance ferroelectric non-volatile memory opens up the possibility of a new type of system design wherein registers are made non-volatile. The new paradigm involves making the register itself non-volatile through the use of ferroelectric memory technology. In this way, the status of some or all registers can be restored simultaneously on power-up.
Ferroelectric memory technology allows the reading or writing of thousands of bits or more simultaneously due to the polarization-based storage mechanism, fast write times and voltage sensing.
At the present time, reliable ferroelectric memories employ controlled timing sequences during read and write operations. While all the circuits presented below theoretically function for any sensing speed and any non-zero ferroelectric capacitor interrogation time, the examples presented use currently standard interrogation and sensing approaches. Where timing diagrams are shown, they may not represent the only useful means of interrogation and sensing.
Finally, ferroelectric memories have shown sensitivity to the ratio of the load capacitance to the effective capacitance of the switching capacitor. This ratio is commonly called the bit/cell ratio. In arrayed ferroelectric memories, the load capacitance due to parasitic terms such as source/drain diffusions and metal-substrate capacitance is often sufficient to meet the desired performance parameters. In some low-density memories, the parasitic load capacitance is not sufficient to create the desired bit/cell ratio. In this case, extra discrete load capacitors can be added. Because ferroelectric memories already have a high dielectric material available, the added load capacitance may be derived from ferroelectric load capacitors. In the case of non-volatile logic, the parasitic load capacitance is negligible when compared to the capacitance of the ferroelectric storage capacitor. As such, the incorporation of extra load capacitance is required. Previous non-volatile logic work makes no mention of this required load capacitance.
In a first embodiment of the invention, a ferroelectric, non-volatile, SR flip-flop includes a set input, a reset input, a Q output, a complementary Q output, a first NAND gate having an internal circuit node, a first input coupled to the set input, a second input coupled to the output, and an output coupled to the complementary Q output, a second NAND gate having an internal circuit node, a first input coupled to the reset input, a second input coupled to the complementary Q output, and an output coupled to the Q output, and a ferroelectric capacitor circuit coupled between the internal node of the first NAND gate and the internal node of the second NAND gate.
The first NAND gate includes a first P-channel transistor having a gate coupled to the first input, a source coupled to a voltage source, and a drain coupled to the output, a second P-channel transistor having a gate coupled to the second input, a source coupled to the voltage source, and a drain coupled to the output, a first N-channel transistor having a drain coupled to the output, a gate coupled to the second input, and a source coupled to the internal circuit node, and a second N-channel transistor having a drain coupled to the internal circuit node, a gate coupled to the first input, and a source coupled to ground.
Alternatively, the first NAND gate includes a first P-channel transistor having a gate coupled to the first input, a source coupled to a first controlled power supply, and a drain coupled to the output, a second P-channel transistor having a gate coupled to the second input, a source coupled to the first controlled power supply, and a drain coupled to the output, a first N-channel transistor having a drain coupled to the output, a gate coupled to the second input, and a source coupled to the internal circuit node, and a second N-channel transistor having a drain coupled to the internal circuit node, a gate coupled to the first input, and a source coupled to a second controlled power supply.
The second NAND gate includes a first P-channel transistor having a gate coupled to the first input, a source coupled to a voltage source, and a drain coupled to the output, a second P-channel transistor having a gate coupled to the second input, a source coupled to the voltage source, and a drain coupled to the output, a first N-channel transistor having a drain coupled to the output, a gate coupled to the second input, and a source coupled to the internal circuit node, and a second N-channel transistor having a drain coupled to the internal circuit node, a gate coupled to the first input, and a source coupled to ground.
Alternatively, the second NAND gate includes a first P-channel transistor having a gate coupled to the first input, a source coupled to a first controlled power supply, and a drain coupled to the output, a second P-channel transistor hav

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