Ferroelectric memory with amplification between sub bit-line...

Details Ferroelectric memory with amplification between sub bit-line... Ferroelectric memory with amplification between sub bit-line...

2007-04-24

2010-06-08

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Interconnection arrangements

Ferroelectric

C365S049120, C365S117000, C365S145000, C365S230030, C365S189150, C365S189060, C365S205000, C365S207000

Reexamination Certificate

active

07733681

ABSTRACT:
A memory capable of suppressing increase of the chip area thereof while increasing a read voltage is obtained. This memory comprises a memory cell array including a plurality of subarrays, a sub bit line arranged on each subarray and provided to be connectable to a main bit line, a storage portion connected between the word line and the sub bit line and a first transistor having a gate connected to the sub bit line and a first source/drain region connected to the main bit line for controlling the potential of the main bit line on the basis of the potential of the sub bit line in a read operation.

REFERENCES:
patent: 2003/0086312 (2003-05-01), Kang
patent: 2005/0141258 (2005-06-01), Kang et al.
patent: 2005/0207203 (2005-09-01), Kang
patent: 2005/0213419 (2005-09-01), Miyamoto
patent: 07-073682 (1995-03-01), None
patent: 2001-229674 (2001-08-01), None
patent: 2003-123466 (2003-04-01), None

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