Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2002-09-13
2004-08-10
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S240000, C257S068000, C257S071000, C257S295000, C257S298000, C257S300000, C257S324000
Reexamination Certificate
active
06773929
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a ferroelectric memory device; and, more particularly, to a ferroelectric memory device including a ferroelectric layer covering all cell region and a method for manufacturing the same.
DESCRIPTION OF RELATED ART
Several studies on utility of a ferroelectric material as a capacitor dielectric, have been developed to overcome a limit of refresh in a conventional dynamic random access memory(DRAM) and to achieve a large capacitance. A ferroelectric random access memory (FORAM) is one of e nonvolatile memory devices that can store information at turn-off state and has a rapid operating speed comparable to that of the DRAM.SrBi
2
Ta
2
O
9
(SBT), Pb (Zr
x
, Ti
1−x
)O
3
(PZT) or (Bi,La)
4
Ti
3
O
12
(BLT)is mainly used as a storage material of FeRAM. The ferroelectric material has a dielectric constant being in the order of 10
2
-10
3
at room temperature and has two stabilized remnant polarization states. Therefore, the ferroelectric material is suitable for applying to a nonvolatile memory device.
A signal is inputted to the nonvolatile memory device adopting ferroelectric material by the change of polarization orientation according to an electric field applied thereto, and a digital signal “1” or “0” is stored therein by an orientation of remnant polarization when an electric field is removed.
In a FeRAM device adopting Sr
x
Bi
y
(Ta
i
Nb
j
)
2
O
9
(hereinafter, referred to as a SBTN), etc, which have perovskite structure, as a ferroelectric layer in a ferroelectric capacitor besides the above-mentioned PZT and SBT, a top/bottom electrode is formed of any one selected from the group consisting of Pt, Ir, Ru, IrO, RuO and Pt-alloy.
FIG. 1
is a conventional equivalent circuit illustrating a FeRAM having one transistor and one capacitor(1T-1C) structure. In
FIG. 1
, ‘C’ denotes a ferroelectric capacitors, ‘Q’ denotes a MOS transistor, ‘WL
1
and WL
2
’ denote word lines connected to a gate of the MOS transistor Q, ‘BL’ denotes a bit line connected to a source/drain region of the MOS transistor, and ‘PL’ denotes a plate line connected to a top electrode of the terroelectric capacitor C.
FIG. 2
is a cross-sectional view of the FeRAM shown in FIG.
1
.
Referring to
FIG. 2
, adjacent two transistors are formed on a semiconductor substrate
11
. A field oxide layer
12
is formed in a predetermined portion of the semiconductor substrate
11
in order to separate two transistors from another two transistors(not shown).
The transistor is formed according to a usual complementary metal oxide semiconductor (CMOS) process. A gate electrode
13
is formed on the semiconductor substrate
11
, and a common connection drain of adjacent two transistors (hereinafter, referred to as a ‘common drain’)
14
A and source
14
B of each transistor are formed in the semiconductor substrate at each side of the gate electrode
13
.
A first interlayer insulating layer
15
is formed and flattened on the semiconductor substrate
11
. The first interlayer insulating layer
15
is formed of a first and a second insulating layer
15
A and
15
B successively deposited. A bit line
17
is connected to the common drain
14
A through a fist contact plug
16
penetrating the first insulating layer
15
A, and the bit line
17
is insulated by the second insulating layer
15
B.
A second contact plug
18
penetrates the first interlayer insulating layer
15
and is connected the source
143
of each transistor and a bottom electrode
19
of a ferroelectric capacitor.
A bottom electrode
19
and a ferroelectric layer
20
are formed on the first interlayer insulating layer
15
to the same size, and a top electric
21
having smaller size than that of the bottom electrode
19
is formed on the ferroelectric layer
20
.
A second interlayer insulating layer
22
covers the ferroelectric capacitor and has opening which exposes the top electrode
21
. A plate line
23
is formed to couple to the top electrode through the opening in the second interlayer insulating layer
22
.
The conventional ferroelectric capacitor of FeRAM cell shown in
FIG. 2
is formed by stacking layers for the bottom electrode
19
, the ferroelectric layer
20
and the top electrode
21
, successively. Thereafter, the top electrode
21
is etched, and the ferroelectric layer
20
and the bottom electrode
19
are etched using other mask different from a mask for forming the top electrode
21
.
In the conventional method, it is difficult to form the top electrode and the bottom electrode to the same size, if the size of a bottom and top electrode is same, a bottom and top electrode can be shorten, so it is hard to obtain safety in a process. Also, it is difficult to form the ferroelectric capacitor with one step etch process because the layers of the ferroelectric capacitor is thick. Furthermore, the etch profile of the ferroelectric capacitor is not vertical but is slant, so there is some limit to reduce the size of the ferroelectric capacitor.
Due to the above-mentioned reason, the size of a top electrode, which determines an electric charge storage capacity of a capacitor, is restricted to be smaller than that of a bottom electrode so that is difficult to obtain enough amount of an electric charge.
In the conventional method, the ferroelectric layer is formed to cover the bottom electrode layer just after forming the bottom electrode layer, so the ferroelectric layer should be etched in an etch process for forming the bottom electrode pattern. In the etch process, the ferroelectric layer is exposed to plasma, and thereby the characteristics of the ferroelectric layer is deteriorated. Therefore, a thermal treatment to recover characteristic of the ferroelectric layer should be performed.
That is, when an etch process for forming the bottom electrode is performed, the portion of ferroelectric layer not covered with the top electrode is inevitably exposed to plasma. At this circumstance of the ferroelectric layer being exposed to plasma, polarization has not have a value of (+) and (−), and according to a condition of the ferroelectric layer being exposed to plasma, a value is fixed into (+) or (−), namely pinning phenomenon is generated. Accordingly, a capacity of the ferroelectric capacitor is reduced extremely.
To solve the above-mentioned problem of the ferroelectric layer being exposed to plasma, the ferroelectric layer is formed on the bottom electrode by a spin coating or liquid source misted chemical deposition (LSMCD) after patterning the bottom electrode.
However, it is difficult to form the ferroelectric layer to a uniform thickness because of a bottom electrode and a topology of sub-layers, which are formed before the bottom electrode. Furthermore, cracks can be generated in a portion of the ferroelectric layer where the bottom electrode is not exist, so it is hard to adopt the spin coating and LSMCD to formed the ferroelectric layer.
In addition, the height of the ferroelectric capacitor formed of the bottom electrode, the ferroelectric layer and the top electrode is over 5500 Å. Therefore, burden of etching is increased, and it becomes more difficult to fill an insulating layer between capacitors and to flat the insulating layers as the cell area is decreased.
With decreasing a cell area, it is hard to form a contact hole between the plate line and the capacitor. There, there is proposed a method of connecting the top electrode directly to the plate line by removing an interlayer insulating layer, which covers the top electrode, with a blanket etching or a chemical mechanical polishing (CMP). However from the above-mentioned method, there may be brought out a problem that a plate line and a bottom electrode are being shorten when the interlayer insulating layer is very thin.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a ferroelectric memory device and manufacturing method forming the same capable of preventing characteristic deterioration of a ferroelectric layer due to an plasma.
It is, therefore,
Oh Sang-Hyun
Seong Jin-Yong
Suh Chung-Won
Birch & Stewart Kolasch & Birch, LLP
Huynh Andy
Hynix / Semiconductor Inc.
Nelms David
LandOfFree
Ferroelectric memory device and method for manufacturing the... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Ferroelectric memory device and method for manufacturing the..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Ferroelectric memory device and method for manufacturing the... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3273423