Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
1999-07-01
2001-05-22
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S240000, C438S393000, C438S239000, C438S250000
Reexamination Certificate
active
06235542
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a method for fabricating a semiconductor memory device, and more particularly to a semiconductor memory device and a method for fabricating the same where a ferroelecric film is used as a dielectric film of a capacitor.
In general, a ferroelectric memory device is nonvolatile and the data stored in the ferroelectric memory device are not removed in power off. However, if the thickness of the dielectric capacitor is very thin, spontaneous polarization is fast occurred so that the ferroelectric memory device is able to read out the data therefrom or write the data therein with high speed. The ferroelectric memory device may constitute memory cells which each thereof is comprised of a transistor and a ferroelectric capacitor so that it is applicable to semiconductor memory device with large capacity. There are typically SrBi2Ta2O9(SBT), PZT and PbZrO3 as the ferroelectric film.
FIG. 1
is a diagram illustrating a method for fabricating a capacitor using SBT film as a dielectric film. Referring to
FIG. 1
, on a semiconductor substrate
11
where a node (not shown) is formed, a first intermediate insulating layer
12
is formed. A glue layer
13
and a conduction layer
14
for storage node are formed on the first intermediate insulating layer
12
in turn. A Ti layer is used for the glue layer
12
and a Pt layer is used for the conduction layer for storage node. A SBT film
15
is deposited on the conduction layer
14
and a conduction layer
16
for plate node is deposed on the SBT film.
The conduction layer
16
for plate node and the SBT film
15
are patterned. Then, a second intermediate insulating layer
17
is deposited over the conduction layer
14
for storage node including the SBT film
15
and the conduction layer
16
for plate. At this time, a spin on glass (SOG) film having a planarization property is used for the second intermediate insulating layer
17
.
The second intermediate insulating layer
17
is etched to expose a selection portion of the conduction layer
16
for plate electrode. An A1 metal layer
18
is formed on the second intermediate insulating layer to be contacted with the exposed conduction layer
16
for plate node. An antireflection film
19
is formed on the Al metal layer
18
and the A1 metal layer
18
and the antireflection film
19
are patterned to form a metal interconnection layer
20
.
However, if a high temperature process such as the second intermediate insulating layer formation process is accomplished following the SBT film deposition, bismuth(Bi) within the SBT film
15
is easily volatile so that the hysterisis property of the SBT film is degraded.
Furthermore, the SBT film
15
is apt to damage by the following process and in depositing the second intermediate insulating layer
17
, the exposed portion of the SBT film
15
and chemicals for forming the second intermediate insulating layer
17
are reacted with each other so that leakage current flows through the SBT film
15
. Therefore, reliability of the memory devices is degraded.
SUMMARY OF THE INVENTION
It is an object of the present invention to prevent Bi within a SBT film being volatile.
It is another object of the present invention to prevent leakage current from generating with a SBT film.
It is an aspect of the present invention to provide a method for fabricating a ferroelectric memory device, comprising the steps of: providing a semiconductor substrate where a transistor having an impurity region is formed; forming a conduction layer for storage node over the substrate; forming a ferroelectric film on the conduction layer; patterning the conduction layer and the ferroelectric film to form a storage node and a dielectric film; forming a protection film for dielectric film over the semiconductor substrate to cover the storage node and the dielectric film; patterning the protection film to expose the dielectric film; and forming a plate node on the dielectric film.
The method further comprises the step of forming a glue layer over the semiconductor substrate before formation of the conduction layer. The glue layer is comprised of one of Ti layer or Ta layer and formed at a thickness of 100 to 1000 Å.
The conduction layer for storage node is comprised of a Pt layer and formed at a thickness of 1000 to 5000 Å.
The method further comprises the step of furnace-annealing the conduction layer at a temperature of 500 to 700° C. during 10 to 60 minutes at ambient of oxygen between conduction layer formation and ferroelectric film formation. The ferroelectric film is formed with spin coating and comprised of SrBi2Ta2O9 (SBT) film.
The formation step of the SBT film includes the steps of: forming a first SBT film over the conduction layer for storage node; drying the first SBT film; rapid-thermally annealing the dried first SBT film; forming a second SBT film on the first SBT film; drying the second SET film; and rapid-thermally annealing the dried second SBT film.
The method further comprises the step of furnace-annealing the first and second SBT films after the rapid-thermally annealing step of the dried second SBT film. The furnace annealing step is carried out at a temperature of 700 to 800° C. during 10 to 60 minutes at ambient of oxygen. The first and second SBT films are first dried at a temperature of 160 to 180° C. during 1 to 5 minutes and then second dried at a temperature of 260 to 280° C. during 1 to 5 minutes.
The rapid-thermally annealing step is carried out at a temperature of 700 to 800° C. during 10 to 60 seconds at ambient of oxygen. The first and second SBT films are formed at a thickness of 800 to 1200 Å.
The protection film for dielectric film is comprised of SrTiO3 and deposited at a temperature of 300 to 550° C. with chemical vapor deposition at a thickness of 500 to 2000 Å.
The plate node is comprised of a Pt layer.
The method further comprises the steps of forming an intermediating insulating layer over the protect-ion film and the plate node; etching the intermediating layer to expose the impurity region of the transistor and the plate node, thereby forming contact holes; and forming a metal interconnection layer over the intermediate insulating layer to be contacted with the impurity region and the plate node through the contact holes.
It is another aspect of the present invention to provide a ferroelectric memory device, comprising: a semiconductor substrate where a transistor having an impurity region; a storage node formed over the substrate; a ferroelectric film formed on the storage node; a plate node formed on the ferroelectric film; and a protection film for dielectric film over the semiconductor substrate to cover the storage node, the dielectric film and the plate node.
The ferroelectric film is comprised of SrBi2Ta2O9 (SBT) film and the protection film is comprised of SrTiO3.
According to the present invention, the protection film of SrTiO3 is formed to cover the dielectric film of SBT film, so that the dielectric film is chemically and thermally stable in the following etching or high temperature thermal oxidation process, thereby preventing Bi within the dielectric film being volatile. Therefore, the hysterisis property of the dielectric film can be improved and leakage current can be reduced.
REFERENCES:
patent: 5382787 (1995-01-01), Takada et al.
patent: 5418389 (1995-05-01), Watanabe
patent: 5516363 (1996-05-01), Azuma et al.
patent: 5527766 (1996-06-01), Eddy
patent: 5541807 (1996-07-01), Evans, Jr. et al.
patent: 5580814 (1996-12-01), Larson
patent: 5635730 (1997-06-01), Sakakibara
patent: 5729054 (1998-03-01), Summerfelt
patent: 5751061 (1998-05-01), Satoh et al.
patent: 5824590 (1998-10-01), New
patent: 5976946 (1999-11-01), Matsuki et al.
patent: 09246510 (1997-09-01), None
patent: 10294433 (1998-11-01), None
Hyundai Electronics Industries Co,. Ltd.
Keshavan Belur
Ladas & Parry
Smith Matthew
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