Ferro-electric capacitor and method of fabrication of the...

Electricity: electrical systems and devices – Electrostatic capacitors – Fixed capacitor

Reexamination Certificate

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C361S303000, C361S305000, C257S295000, C257S296000

Reexamination Certificate

active

06643117

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to a method of fabrication of a ferro-electric capacitor and growing a PZT layer on a substrate. The present invention is also related to a ferro-electric capacitor and a 3D-capacitor.
2. Description of the Related Art
There is a development in the art of non-volatile memories based on ferro-electric capacitors (FERAM-structure). In this development PZT films are an important candidate material. Such PZT films are ferro-electric layers comprising at least platinum, zirconium and titanium. Usually they are in the form of: Pb (Zr, Ti)O3 or (PbX) (Zr TiY)O3 where X=La and Y=Ta, are in small concentration as dopants.
A ferro-electric PZT based capacitor is formed by sandwiching a PZT layer between a first and a second electrode, the first electrode being a bottom electrode, the second electrode being a top electrode.
The principal advantage of PZT materials is their relatively low (500-600° C.) crystallization temperatures which are compatible with a base line CMOS process and their high remnant polarization.
As the deposition of a PZT layer directly on a bottom electrode such as a Pt-layer leads to poor fatigue performance of the capacitor, it was suggested to have a conductive oxide layer first deposited on the Pt-layer before the deposition of the PZT layer. This conductive oxide can be a unary oxide having a rutile crystal structure such as IrO
2
, RuO
2
or OsO
2
or a complex oxide having a perovskite structure such as (La,Sr) CoO
3
.
For the synthesis of ferro-electric PZT layers, use is often made of a two-step process:
an amorphous layer is deposited, for instance by sol-gelor CVD or related techniques,
this amorphous layer is converted into a ferro-electric layer having a perovskite crystal structure by a thermal treatment (crystallization).
While the growth of oriented PZT layers is in principal facilitated by the use of perovskite electrodes, unary oxides are in practice preferred because they are readily synthesized by reactive sputtering. RuO2 has received the most attention in this respect because of its relatively low resistivity (50 u&OHgr;cm, the lowest of the rutile type oxides), excellent diffusion barrier properties, and proven compatibility with silicon technology.
In order to obtain PZT ferro-electric layers showing high quality hysteresis loops and ferro-electric switching properties, it may be advantageous to achieve a strongly preferential (111) orientation of: the grains making up the PZT layer.
This goal can be achieved by using a template layer having a (111) orientation such as a sputtered Pt layer with the (111) orientation.
In order to achieve the desired (111) orientation in the PZT layer, a conductive oxide is commonly grown under conditions so as to obtain a columnar microstructure on top of the so-called template layer which has the property that it can be deposited with a strongly preferred orientation. In this type of microstructure there is a fixed orientation relationship between the grains of the Pt layer and the grains of the conductive oxide layer.
So in other words such conductive oxide layer with a columnar microstructure can transmit the orientation of the underlying Pt layer to thereby assure that the PZT layer formed on this conductive oxide layer will have, after crystallization, the same orientation as the underlying PT layer. Because the grains of the Pt are strongly preferentially (111) oriented, this means that the grains of the conductive oxide layer will be preferentially oriented as well. Because the grains of the PZT layer grown subsequently will again tend to have a fixed orientation relationship with the conductive oxide, it is possible in this way to grow highly oriented PZT layers having a (111) orientation.
However, this conventional approach described here above has several drawbacks.
Firstly, the need to make use of a template layer such as Pt represents a considerable process complication. However the template layer is needed because without it, the conductive oxide has the property to grow with random or mixed structure.
Secondly, the columnar structure of both the first layer, i.e. the template layer and the second layer, i.e., the conductive oxide layer leads to inferior diffusion barrier properties of these layers. These diffusion barrier properties are necessary to protect the layers lying under the PZT layers against the in diffusion of oxygen during the growth of the PZT layer. This is of particular importance in a configuration where the bottom electrode of the capacitor is formed on a via connection, connecting said bottom electrode with the terminal of an active device, e.g., a MOSFET. This out-diffusion of oxygen can lead to a degradation of the electrical properties, particularly the conductivity, of this via connection.
Thirdly, the growth of a PZT layer on a bottom electrode with a columnar structure can have, depending on the application, a further disadvantage as it leads to PZT layers with small grain sizes, typically, 100 to 200 nm lateral dimension. This small grain size is the result of the high nucleation rate of PZT on columnar layers during the crystallization treatment. This high nucleation rate is due to the large surface roughness of columnar layers. This surface roughness is caused by the grains of the conductive oxide, which have the tendency to form facets. These facets form fixed angles with respect to the growth direction. Due to this effect, layers with smaller grains have a lower surface roughness. A higher surface roughness makes the formation of a nucleus with the desired crystal structure energetically favorable during crystallization because the nucleation can take place in a recess at the surface between two adjacent grains thereby minimizing the required amount of surface that needs to be created for formation of the nucleus. The small grained PZT layers obtained on columnar electrode layers renders the fabrication of ferro-electric devices on a single PZT grain impossible. Ferro-electric capacitors comprising a PZT layer being composed of a single grain are known to exhibit superior properties such as abrupt ferro-electric switching, low leakage current and high endurance compared to capacitors comprising multiple grains as such multiple grain capacitors incorporate grain boundaries.
Fourthly, fabrication of 3D capacitors using a columnar bottom electrode leads to an undesirable orientation of the PZT grown on the side walls. This misorientation implies that the purpose of 3D-capacitor fabrication, namely a gain in the amount of switchable charge per unit area on the wafer, is defeated. To avoid this problem, a new method has to be developed which does not employ the orientation of the bottom electrode grains as a means to control the orientation of the PZT grains.
SUMMARY OF THE INVENTION
The present invention aims to suggest a method of growing a PZT layer on a bottom electrode and accordingly a method of fabrication of a ferro-electric capacitor which do not have the drawbacks of the state of the art.
According to one embodiment of the invention, a ferro-electric capacitor comprises a first electrode comprising at least a layer of a conductive oxide having at least two sub-layers of individual grains, wherein individual grains of a top sub-layer of the two sub-layers are oriented randomly. The capacitor further comprises a second electrode that is isolated from said first electrode. The capacitor further comprises a ferro-electric PZT layer that is sandwiched between said first electrode and said second electrode.
In another embodiment, the invention provides a method of making the ferro-electric capacitor by growing a PZT layer on a conductive oxide layer formed on a substrate The method comprises forming at least two sub-layers of individual grains to comprise said oxide layer. The method further comprises causing the top sub-layer of the two sub-layers to have a random orientation. The method further comprises placing a PZT layer between the two sub-layers and an electrod

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