Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2001-09-10
2003-11-11
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S240000, C438S393000, C438S396000, C257S295000, C257S310000, C257S306000, C257S308000, C257S532000, C361S303000
Reexamination Certificate
active
06645779
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a ferroelectric random access memory (FeRAM) and, more particularly, to a method for forming the FeRAM using an aluminum oxide layer as an oxygen diffusion barrier.
DESCRIPTION OF THE PRIOR ART
A ferroelectric random access memory (FeRAM) is a nonvolatile semiconductor memory device with a highly integrated dynamic random access memory (DRAM), the speedy information processing of a static random access memory (SRAM), and the information storing function of a flash memory. As compared with a conventional flash memory and an electrically erasable programmable read only memory (EEPROM), it has a relatively low operational voltage and an operational speed that is about 1000 times faster.
When voltage is applied to a DRAM capacitor, which includes a dielectric layer such as a SiO
2
layer or a SiON layer, and then the voltage supply is terminated, the charges in the DRAM capacitor are discharged so that data stored in the DRAM are lost.
Being different from the DRAM capacitor, a ferroelectric capacitor in the FeRAM maintains previously stored data by the remnant polarization of a ferroelectric material even if the power supply is terminated.
FIG. 1
is a circuit diagram illustrating a memory cell structure of a conventional FeRAM device including one transistor and one ferroelectric capacitor. A pass-gate transistor (Tr) is connected to a bit line (BL) and a capacitor (C), and the capacitor (C) functions as a charge storage element through a first electrode and a second electrode which are respectively connected to a plate line (PL) and the transistor (Tr). Also, a ferroelectric layer is formed between the first electrode and the second electrode.
The FeRAM device is similar to the DRAM device in that a capacitor and a transistor are connected to a word line and a plate line, respectively. However, the FeRAM device is different from the DRAM device in that the capacitor has a thin ferroelectric layer and the plate line is not connected to ground voltage or a fixed voltage, e.g., ½ Vcc, and each cell is connected to a separate plate line so that power can be applied to the separate plate line on a cell-by-cell basis.
FIG. 2
is a graph showing a hysteresis loop of a ferroelectric capacitor. In
FIG. 2
, positive voltage is defined when the potential of the plate line is higher than that of the bit line and remnant polarization at points “a” and “c”, are defined to data “1” and “0”, respectively.
If the transistor is turned on and a negative voltage level is applied to the plate line “PL”, then a negative voltage is also applied to the ferroelectric capacitor and a charge variation passes through point “d” in the hysteresis loop. After that, in case of turning the applied voltage to “0 V”, polarization value goes to point “a” and the data “1” is stored. Meanwhile, a positive voltage level is applied to the ferroelectric capacitor, the charge variation passes through point “b”, a polarization value goes to point “c” by turning the applied voltage to “0 V” and the data “0” is stored.
When the voltage is applied to the ferroelectric capacitor, data reading process is carried out by detecting a voltage variation on the bit line. That is, if a positive voltage is applied to the capacitor, in case the data is “0”, the charge variation of &Dgr; Q
0
is detected. That is, the charge variation on the bit line is determined by information stored on the capacitor.
The charge variation due to the remnant polarization of the ferroelectric capacitor changes a voltage level on the bit line. Typically, parasite capacitance “Cb” exists on the bit line itself. When the transistor is turned on and a memory to be read out is selected, charges of as much as &Dgr; Q
1
or &Dgr; Q
0
are outputted. Bit line voltages “V
1
” and “V
0
” are acquired by dividing the &Dgr; Q
1
and the &Dgr; Q
0
with the sum of bit line capacitance (Cb) and ferroelectric capacitor (C) capacitance “Cs”, respectively and these values are given by:
V
1
=&Dgr;
Q
1
/(
Cb+Cs
)
V
0
=&Dgr;
Q
0
/(
Cb+Cs
)
Therefore, the potential on the bit line is varied according to the difference between the data “1” and “0”. When the transistor is turned on by applying a voltage level to the word line, the potential on the bit line is changed to the “V
1
” or the “V
0
”. In order to determine whether potential on the bit line is in a voltage level of “V
1
” or “V
0
”, a reference voltage (Vref), which is set to a specific voltage level between the voltage levels “V
1
” and “V
0
”, is used.
SrBi
2
Ta
2
O
9
(hereinafter, referred to as an SBT), (Bi, La)
4
Ti
3
O
12
(hereinafter, referred to as a BLT) or Pb(Zr, Ti)O
3
(hereinafter, referred to as a PZT) thin layer is mainly used as a dielectric material in the FeRAM. Since a ferroelectric material is of crystallized structure, a bottom material disposed thereunder is important in growing the ferroelectric material. That is, in the ferroelectric capacitor, the electrode is largely affected by the ferroelectric characteristics, so there is a requirement for sufficiently low resistance, a small lattice mismatch between the ferroelectric material and the electrode, a high heat-resistance, a low reactivity, a high oxidation barrier characteristic and a good adhesion between the electrode and the ferroelectric material.
Especially, the ferroelectric memory device manufacturing process incorporates a high thermal process. Accordingly, a polysilicon layer, which has been used in a DRAM device, cannot be used as an electrode, because the polysilicon layer may be oxidized in forming a ferroelectric layer, such as the SBT, or in other thermal processes.
Therefore, in a conventional method, a metal layer is used as an interconnection layer in the FeRAM device, connecting a top electrode of the ferroelectric capacitor to a metal oxide semiconductor field effect transistor (MOSFET).
FIG. 3
is a cross sectional view showing a FeRAM device according to the prior art. A transistor having a gate insulating film
12
, a gate electrode
13
and a source/drain region
14
is formed in a semiconductor substrate
10
where a field oxide layer
11
is formed. A first interlayer insulating film
15
is formed over the transistor and a tungsten or a polysilicon plug
16
is buried in a contact hole exposing the source/drain region
14
of the transistor through a selective etching process of the first interlayer insulating film
15
. Also, an Ir oxidation barrier film
17
is formed on the plug
16
and a Si
3
N
4
film spacer
18
is formed on the sidewalls of the Ir oxidation barrier film
17
. A bottom electrode
19
of a ferroelectric capacitor is formed on the Ir oxidation barrier film
17
and the Si
3
N
4
film spacer
18
, and a ferroelectric film
20
, a top electrode
21
, and a second interlayer insulating film
22
are, in this order, formed on the entire structure. To form the ferroelectric film
20
for charge storage, a thermal treatment process is carried out at a high temperature of approximately 650° C. to 750° C. in an oxygen atmosphere. During this process, oxygen may penetrate into the ferroelectric film
20
, the bottom electrode
19
and the Ir oxidation barrier film
17
. If the plug
16
, which forms an electrically connecting path between the capacitor and the transistor, is oxidized by the penetrating oxygen, the oxidized plug may cause an electrical disconnection between the capacitor and the transistor.
FIG. 4
is a cross sectional view showing oxygen oxidation paths (“a”, “b”) in the prior art ferroelectric capacitor of FIG.
3
. Although, in the prior stacked capacitor, the oxidation of the plug
16
in the vertical direction “a” is prevented by using the Ir oxidation barrier film
17
, the oxygen can easily penetrate into the plug
16
in the horizontal direction indicated by “b” through an interface between the Ir oxidation barrier film
17
and the first interlayer insulating film
15
. Further the penetrating oxygen oxidizes a contacted part between the plug
16
and the Ir oxidation barrier
17
.
Ac
Jacobson & Holman PLLC
Keshavan Belur V.
Smith Matthew
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