Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2005-08-16
2005-08-16
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S108000, C438S111000, C438S113000, C438S125000, C438S109000, C257S659000, C257S660000, C257S704000, C257S682000
Reexamination Certificate
active
06929974
ABSTRACT:
A microdevice (20, 120, 220) having a hermetically sealed cavity (22, 122, 222) to house a microstructure (26, 126, 226). In one embodiment, the microdevice (20) comprises a substrate (30), a cap (50) and an isolation layer (70). The substrate (30) has a plurality of conductive traces (38) formed on at least a portion of its top side (32) and outer edge (36). The conductive traces (38) provide electrical conductivity to the microstructure (26). The isolation layer (70) is attached between an outer edge of a sidewall (54) of the cap (50) and the plurality of conductive traces (38). The cavity (22) is at least partially defined by a recess (56) in the cap (50). There is also a microdevice (120) comprising a substrate (130), a cap (150) and a plurality of via covers (170). The substrate (130) has conductive vias (196) that terminate at a contact point (146) within the sealed cavity (122). The via covers (170) are attached to the substrate (130) to provide a hermetic seal. There is a further microdevice (220) comprising a substrate (230), a cap (250), and a plurality of conductive members (270). The cap (250) has conductive vias (296) that terminate at the conductive members (270). The conductive members (270) are electrically connected to the microstructure (226). There are also methods of forming the microdevice (20, 120, 220).
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Ding Xiaoyi
Frye Jeffrey J.
Anya Igwe U.
Mancini Brian
Miller Thomas V.
Smith Matthew
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