Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Converging with plural inputs and single output
Reexamination Certificate
2000-10-24
2001-10-09
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Converging with plural inputs and single output
C327S403000, C327S030000, C327S099000, C327S051000, C327S205000, C365S189080, C365S190000
Reexamination Certificate
active
06300816
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the design of integrated circuits and more particularly to sense amplifiers.
2. Description of the Background Art
Many systems on an integrated circuit are designed to respond differently depending upon whether their input voltages are considered HIGH or LOW. Sometimes, an input voltage must be modified to conform to the HIGH or LOW state (e.g., during the period when the input voltage transitions between states). Sense amplifiers are circuits that detect a small voltage differential and increase or decrease the voltage to a level required by the system. An example of a system that utilizes sense amplifiers is a computer memory circuit. Information stored in the memory cells of a memory chip using sense amplifiers can be retrieved much faster than from a memory chip without sense amplifiers.
As shown in
FIG. 1
, a common static random access memory (SRAM) configuration generally designated
100
includes an array
105
of memory cells
110
. Each memory cell
110
is connected to a word line
115
, a bit line B
120
, and a complement of the bit line, {overscore (B)}
145
. The memory cells
110
connected to each of the word lines
115
define a memory cell array row
125
, and the memory cells connected to each of the bit line B
120
and a corresponding complement of the bit line {overscore (B)}
145
define a memory cell array column
130
. Each memory cell
110
stores information in the form of a voltage charge representing a logic value of LOW or HIGH. A voltage level equal to V
DD
represents the logic value of HIGH and V
SS
represents the logic value of LOW.
Bit lines B
120
and {overscore (B)}
145
are connected to an equalization and precharge circuit
150
. The precharge component of the equalization and precharge circuit
150
initially charges bit lines B
120
and {overscore (B)}
145
to the voltage level of V
DD
. The equalization component of the equalization and precharge circuit
150
ensures that the voltages on bit lines B
120
, &ngr;
B
, and {overscore (B)}
145
, &ngr;
{overscore (B)}
, are initially at the same level.
The word lines
115
are connected to a row decoder
155
. When a memory cell
110
′ is accessed, the row decoder
155
selects and changes the voltage of a word line
115
′ corresponding to memory cell
110
′. A changed voltage signal (e.g., LOW to HIGH) from the word line
115
′ allows memory cell
110
′ to communicate with bits lines B
120
′ and {overscore (B)}
145
′. If memory cell
110
′ stores a logic value of HIGH, then &ngr;
{overscore (B)}
will remain at HIGH and &ngr;
{overscore (B)}
will decrease to LOW. If memory cell
110
′ stores a logic value of LOW, then &ngr;
B
will decrease to LOW and &ngr;
{overscore (B)}
will remain at HIGH.
Bit lines B
120
and {overscore (B)}
145
are connected to a sense amplifier
160
which detects and amplifies the difference in voltage between &ngr;
B
and &ngr;
{overscore (B)}
. Depending on the difference between &ngr;
B
and &ngr;
{overscore (B)}
, the sense amplifier
160
will output either V
DD
or V
SS
.
Connected to the sense amplifier
160
is a column decoder
165
. The column decoder
165
, like the row decoder
155
, includes a combination of logic circuits that select a logic signal from either one or a set of the memory cell array columns
130
for final output from SRAM
100
.
The prior art described above suffers from a number of limitations. To store more information on a single memory chip, smaller memory cells are used. Smaller memory cells, however, use smaller transistors, which have less driving capability, resulting in a longer time for &ngr;
B
and &ngr;
{overscore (B)}
to reach distinct HIGH or LOW voltage levels. To reduce the time required to read a memory cell, sense amplifiers are used to quickly detect the small voltage difference between &ngr;
B
and &ngr;
{overscore (B)}
without having to wait for &ngr;
B
and &ngr;
{overscore (B)}
to reach definite HIGH or LOW voltage levels. However, when &ngr;
B
and &ngr;
{overscore (B)}
reach definite HIGH or LOW voltage levels before the operation of the sense amplifier, the operation of the sense amplifier is not required and consumes unnecessary power.
What is needed is a sense amplifier design that overcomes the shortfalls of the sense amplifier designs known in the art.
SUMMARY OF THE INVENTION
The invention provides a circuit for discriminating between the states of complementary first and second input signals. The input signals are either in distinctly complementary states, in indeterminate states, or in distinctly non-complementary states. The circuit includes a logic gate circuit, a signal amplifying circuit and an input select circuit.
The logic gate circuit determines whether the complementary input signals are in distinctly complementary states. The logic gate circuit produces a first output when the input signals are in distinctly non-complementary states and a second output when the input signals are in distinctly complementary states. In one embodiment of the invention, a pair of Schmitt triggers ensure that the logic gate's output does not change when the input signals are in indeterminate states.
The signal amplifying circuit output varies depending upon whether the first input signal is greater than, equal to, or less than the second input signal. To conserve power, the signal amplifying circuit is enabled in response to the first output of the logic gate circuit and disabled in response to the second output of the logic gate circuit. Thus, the signal amplifying circuit is disabled when signal amplification is no longer needed in the case where the first and second input signals are distinctly complementary.
The input select circuit output provides the output for the circuit. The input select circuit output is dependant upon the signal amplifying circuit output when the signal amplifying circuit is enabled and either the first input signal or the second input signal when the signal amplifying circuit is disabled.
Other advantages and features of the present invention will be apparent from the drawings and detailed description as set forth below.
REFERENCES:
patent: 5155397 (1992-10-01), Fassino et al.
patent: 5157291 (1992-10-01), Shimoda
patent: 5889419 (1999-03-01), Fischer et al.
patent: 6091277 (2000-07-01), Fujii
patent: 6215339 (2001-04-01), Hedberg
Carr & Ferrell LLP
Cunningham Terry D.
Malino Morgan E.
Nguyen Long
Rosun Technologies, Inc.
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