Amplifiers – With pilot frequency control means
Reexamination Certificate
2002-01-17
2003-05-20
Tokar, Michael (Department: 2819)
Amplifiers
With pilot frequency control means
C330S149000, C330S151000
Reexamination Certificate
active
06566945
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a feedforward amplifier for amplifying a radio frequency signal and the like with suppressing signal error.
BACKGROUND ART
A feedforward amplifier that implements low error characteristic by feedforward error compensation is often used in radio frequencies such as VHF, UHF and microwave bands as an amplifier that can achieve low error amplification.
The feedforward error compensation scheme can achieve good error compensation principally, and has an advantage of being able to configure an amplifier with very low error. However, it has a problem of deteriorating its error characteristics because of reduction in the error compensation amount of a feedforward system caused by variations in the amplifier characteristics due to ambient temperature or secular changes.
To solve the problem, a system is proposed that introduces a pilot signal into a loop constituting the feedforward error compensation system, and controls the amplifier and loop of the feedforward system by detecting the pilot signal.
FIG. 1
is a block diagram showing a configuration of a conventional feedforward amplifier disclosed in Japanese patent application laid-open No. 4-70203, for example. In this figure, the reference numeral
1
designates an input terminal of the feedforward amplifier;
2
designates a pilot signal oscillator for generating a first pilot signal (frequency f
1
);
3
designates a combiner for combining an input signal supplied from the input terminal
1
with the first pilot signal;
4
designates a feedforward system;
5
designates a pilot signal oscillator for generating a second pilot signal (frequency f
2
);
6
designates an error detection loop for amplifying the input signal supplied from the combiner
3
, and for extracting an error component involved in the amplification of the input signal; and
7
designates an error rejection loop for canceling out the error component included in the input signal.
The reference numeral
8
designates a divider for dividing the input signal plus the first pilot signal combined by the combiner
3
into two paths;
9
designates a vector regulator for electrically regulating passing amplitude and phase of the input signal distributed by the divider
8
;
10
designates a combiner for combining the input signal supplied from the vector regulator
9
with the second pilot signal;
11
designates a main amplifier for amplifying the input signal passing through the combining by the combiner
10
;
12
designates a delay circuit for delaying the input signal distributed by the divider
8
; and
13
designates a dividing combiner for dividing the input signal output from the main amplifier
11
into two portions, for supplying a first portion of the input signal to a delay circuit
14
, and for extracting the error component produced by the main amplifier
11
by canceling out the input signal component of a second portion of the input signal by combining the second portion of the input signal with the input signal delayed by the delay circuit
12
.
The reference numeral
14
designates the delay circuit for delaying the input signal supplied from the dividing combiner
13
;
15
designates a divider for distributing the error component extracted by the dividing combiner
13
to two paths;
16
designates a vector regulator for electrically regulating the passing amplitude and phase of the error component distributed by the divider
15
;
17
designates an auxiliary amplifier for amplifying the error component output from the vector regulator
16
; and
18
designates a combiner for combining the input signal delayed by the delay circuit
14
with the error component after the amplification, thereby canceling out the error component included in the input signal.
The reference numeral
19
designates a pilot signal detector for detecting the first pilot signal from the output signal of the divider
15
;
20
designates a control circuit for controlling the vector regulator
9
such that the power level (signal level) of the first pilot signal detected by the pilot signal detector
19
becomes minimum;
21
designates a divider for distributing the input signal, the error component of which is canceled out by the combiner
18
, to two paths;
22
designates a pilot signal detector for detecting the second pilot signal from the input signal distributed by the divider
21
;
23
designates a control circuit for controlling the vector regulator
16
such that the power level (signal level) of the second pilot signal detected by the pilot signal detector
22
becomes minimum;
24
designates a bandpass filter (abbreviated to BPF from now on) for eliminating the first pilot signal from the input signal distributed by the divider
21
; and
25
designates an output terminal of the feedforward amplifier.
Next, the operation will be described.
First, when the combiner
3
combines the input signal supplied from the input terminal
1
with the first pilot signal, the error detection loop
6
amplifies the input signal, and detects the error component involved in the amplification of the input signal.
Specifically, the divider
8
of the error detection loop
6
divides the input signal supplied from the combiner
3
to two paths. Then, the vector regulator
9
electrically regulates the passing amplitude and phase of a first portion of the input signal. After that, the combiner
10
combines the input signal with the second pilot signal, and the main amplifier
11
amplifies the input signal passing through the combining by the combiner
10
.
On the other hand, the delay circuit
12
delays a second portion of the input signal divided by the divider
8
by a predetermined time period, and supplies it to the dividing combiner
13
.
The dividing combiner
13
, receiving the input signal amplified by the main amplifier
11
, divides the input signal into two portions, and supplies the first portion of the input signal to the delay circuit
14
. On the other hand, it combines the second portion of the input signal with the input signal supplied from the delay circuit
12
. Thus, it extracts the error component the main amplifier
11
generates by canceling out the input signal component in the input signal after amplification.
Here, the error detection loop
6
performs optimization as follows.
Specifically, when the pilot signal detector
19
detects the first pilot signal from the output signal of the divider
15
, the control circuit
20
controls the vector regulator
9
such that the power level of the first pilot signal becomes minimum, thereby optimizing the error detection loop
6
.
The error rejection loop
7
cancels out the error component in the input signal when the error detection loop
6
extracts the error component from the input signal.
Specifically, when the vector regulator
16
of the error rejection loop
7
electrically regulates the passing amplitude and phase of the error component distributed by divider
15
, and then the auxiliary amplifier
17
amplifies the error component, the combiner
18
combines the amplified error component with the input signal delayed through the delay circuit
14
, thereby canceling out the error component in the input signal. Thus, the error component in the input signal is canceled out by combining the input signal with the error component with the identical amplitude and opposite phase to those of the error component in the amplified input signal.
The error rejection loop
7
performs optimization as follows.
Specifically, when the pilot signal detector
22
detects the second pilot signal in the output signal of the divider
21
, the control circuit
23
controls the vector regulator
16
such that the power level of the second pilot signal becomes minimum, thereby optimizing the error rejection loop
7
.
The BPF
24
rejects the first pilot signal included in one of the two portions output from the divider
21
that divides the combined input signal fed from the combiner
18
into two paths, and supplies the output terminal
25
only with the input signal comp
Horiguchi Kenichi
Ikeda Yukio
Kunugi Satoshi
Nakayama Masatoshi
Sakai Yuji
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