Feedback source coupled FET logic

Details Feedback source coupled FET logic Feedback source coupled FET logic

1988-01-19

1990-05-08

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307450, 307356, 307554, 307310, H03K 1714

Patent

active

049241168

ABSTRACT:
A feedback source coupled FET logic (FSCL) circuit having an internal reference voltage provided by the output of one FET of a pair of FET's, connected via a source follower FET to the input of the other FET of the pair. FSCL logic circuitry has advantages over known source coupled FET logic (SCFL) circuitry in that FSCL has higher density of functions for a given area of integrated circuitry, lower voltage drift with temperature change, higher voltage gain, higher noise margin, and larger fanout loading. The output of one FET, via a source follower FET, is connected to the input of the other FET of the pair.

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patent: 4661725 (1987-04-01), Chantepie
Katsu et al., "A GaAs Monolithic Frequency Divider Using Source Coupled FET Logic", IEEE TELD, vol. EDL-3, No. 8, Aug. 1982, pp. 197-199.
Welbourn et al., "A High Speed GaAs 8 Bit Multiplexer Using Capacitor-Coupled Logic", IEEE JSSC, vol. SC-18, No. 3, Jun. 1983, pp. 359-364.
Zuleeg et al., "Femtojoule High-Speed Planar GaAs E-JFET Logic" IEEE TELD, vol. ED-25, No. 6, Jun. 1978, pp. 628-639.
Microelectronic Circuits, by Sedra & Smith (1982).

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