Electrical pulse counters – pulse dividers – or shift registers: c – Shift register – Particular input circuit
Patent
1995-09-12
1997-01-21
Wambach, Margaret Rose
Electrical pulse counters, pulse dividers, or shift registers: c
Shift register
Particular input circuit
377 81, 327164, H03K 384
Patent
active
055966179
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The present invention relates to a feedback shift register for generating digital signals representing pseudo-random number sequences comprising n-stages and exclusive OR-circuits in the feedback logic, as well as comprising a clock-pulse generator.
A. Wolf "Me.beta.technik fur das BISDN" [Measuring Technique for the BISDN], VDE Publishers, 1992, pp. 72-75 or U. Tietze/Ch. Schenk "Halbleiter-Schaltungstechnik" [Semiconductor Circuit Engineering], Springer Publishers 1976, pp. 590-593 disclose one such feedback shift register. FIG. 1 depicts a known shift register 1 of this type that includes five stages 2, 3, 4, 5 and 6, each constituted by for example, a D-flip-flop. As is apparent from FIG. 1, the shift register 1 goes through a feedback loop, an exclusive OR-gate 7 being arranged between the stages 3 and 4. The operation of this register can be expressed by the following generator polynomial G.sub.KKF (x):
This generator polynomial G.sub.KKF (x) is a so-called irreducible polynomial with the degree g=5; the period of a 2.sup.5 -m-sequence able to be generated with it as a pseudo-random number sequence amounts to 2.sup.g -1=31.
For the sake of having a simplest possible description, neither the clock-pulse generator common to all stages nor the customary blocking protection are depicted in the case of the known shift register shown in FIG. 1. In the case of the known shift register, all stages receive the same clock signal, through which means the contents i.sub.1 (x).x.sup.0, i.sub.2 (x).x.sup.1, etc. of the individual stages 2 through 6 change with every clock signal. The contents of the individual stages can be expressed by the polynomial I(x) indicated in the following equation (2): .multidot.i.sub.3 +x.sup.1 .multidot.i.sub.2 +x.sup.0 .multidot.i.sub.1( 2 )
In a generally known manner, the contents of the shift register make up the rows of a binary Galois field, and can generally be expressed by the following relation (3) depicted in FIG. 2 result then for the contents of the stages 2 through 6 when a shift register in accordance with FIG. 1 is used. From x.sup.31 on, the states of the individual stages 2 through 6 repeat themselves because of the period of 31 of the 2.sup.5 -m-sequence. One obtains the 2.sup.5 -m-sequence as a binary sequence of numbers:
An inadequacy of the digital signals produced with the known shift register is that they have a period of 2.sup.n -1 where n denotes the number of stages of the shift register. Thus in the case of the depicted 2.sup.5 -m-sequence the period duration is 31. Therefore, the thus generated digital signals are not easily suited for further digital processing using customary digital measured-value processing devices. This is true, for example, when a fast Fourier transform is supposed to be made, for which it is a condition that the data record has 2.sup.n values.
SUMMARY OF THE INVENTION
The present invention proposes a feedback shift register for generating digital signals representing pseudo-random number sequences, which always supply a full data record 2.sup.n regardless of the number of its n-stages.
In the case of a feedback shift register of the type according to the invention indicated at the outset, this objective is achieved in that the clock-pulse generator is linked with the n-stages via a controllable gate circuit, which blocks one clock pulse of 2.sup.n clock pulses of the clock-pulse generator in each case.
An essential advantage of the shift register according to the invention consists in that as the result of the blocking or suppressing of one clock pulse from a series of 2.sup.n clock pulses of the clock-pulse generator in each case, the shift register is not clocked further for one pulse of the clock pulse generator, so that the stages of the shift register do not change their state for this one clock pulse; as a result, the generated digital signals are extended by one bit and the thus acquired pseudo-random number sequence or the thus acquired digital signals have a period duration of 32, when the con
REFERENCES:
patent: 3715508 (1973-02-01), Blasbalg
patent: 3751648 (1973-08-01), Wu
patent: 3984668 (1976-10-01), Zetterberg et al.
patent: 5289518 (1994-02-01), Nakao
IEEE Proceedings/Computers and Digital Techniques, Jan. 1988, UK, 135 No. 1, Part E, pp. 67-69: Generators for Sequences with Near-Maximal Linear Equivalence.
A. Wolf: "Messtechnik fur das BISDN", VDE-Verlag GmbH, Berlin, pp. 72-75.
U. Tietze et al.: Halbleiter-Schaltungstechnik, Springer-Verlag, Berlin, DE, 1976, pp. 590-593.
Ahrweiler Hans W.
Wolf Andreas
Siemens Aktiengesellschaft
Wambach Margaret Rose
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