Oscillators – Automatic frequency stabilization using a phase or frequency... – With intermittent comparison controls
Reexamination Certificate
2001-10-12
2003-09-16
Mis, David C. (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
With intermittent comparison controls
C331S00100A, C331S016000, C331S017000, C331S018000, C331S025000, C331SDIG002, C327S156000, C327S157000, C327S159000
Reexamination Certificate
active
06621354
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to feedback control systems and, more particularly, to phase-locked loops.
2. Description of the Related Art
A phase-locked loop is a particular type of feedback control system that maintains an output signal in a specific phase relationship with a reference signal. Phase-locked loops are vital parts of a wide variety of electronic systems (e.g., frequency synthesizers, analog and digital modulators, clock recovery circuits and direct digital synthesizers) and the basic structure of conventional phase-locked loops has been described (e.g., see U.S. Pat. Nos. 6,222,421 and 6,252,466 respectively issued Apr. 24, 2001 and Jun. 26, 2001).
Conflicting demands are placed on the selection of a loop bandwidth for a phase-locked loop. The loop bandwidth is preferably set low to filter out input-related spurious tones and phase noise to thereby meet required system spectral and noise performances. The loop bandwidth, however, is preferably set high to achieve fast switching time in response to a frequency change of the reference signal. Accordingly, the selection of loop bandwidth has typically been a compromise which degrades one or more phase-locked loop performance parameters.
SUMMARY OF THE INVENTION
The present invention is directed to feedback methods and systems that achieve rapid switching of oscillator frequencies without compromising operational feedback loop bandwidths that filter out spurious tones and phase noise to thereby enhance loop spectral and noise performance.
These goals are realized with feedback methods that respond to frequency changes in a reference signal by:
a) providing an open-loop drive current to drive a feedback signal towards the reference signal,
b) detecting that the feedback signal is within a predetermined acquisition range of the reference signal; and
c) terminating the drive current and closing the feedback control loop to lock the feedback signal to the reference signal.
In an embodiment of the invention, the closed loop is initially configured with a first feedback bandwidth and is subsequently reconfigured with a second steady-state feedback bandwidth that is less than the first feedback bandwidth.
The invention also provides a feedback control systems that practice the invention's methods
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patent: 4749961 (1988-06-01), Kato et al.
patent: 6222421 (2001-04-01), Klyose
patent: 6252466 (2001-06-01), Kawamura
patent: 6342818 (2002-01-01), Segawa et al.
patent: 6522206 (2003-02-01), Kornblum et al.
patent: 6549079 (2003-04-01), Crook
Byrd, David, et al., Application Note 1000, National Semiconductor Corporation, Jul., 1995, pp. 1-5 “A Fast Locking Scheme For PLC Frequency Synthesis”.
LM2306 / LMX2316 / LMX2326 Low Power Frequency Synthesizer Data Sheet, National Semiconductor Corporation, Apr., 2001, p. 1-18.
Crook David T.
Kornblum John J.
Analog Devices Inc.
Koppel, Jacobs Patrick & Heybl
Mis David C.
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