Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-10-21
2002-09-17
Elms, Richard (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185290, C365S218000
Reexamination Certificate
active
06452840
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the art of microelectronic integrated circuits. More specifically, this invention relates to the art of erasing microelectronic flash Electrically Erasable Programmable Read-Only Memory (EEPROM) devices. Even more specifically, this invention relates to a method of erasing microelectronic flash Electrically Erasable Programmable Read-Only Memory using a feedback mechanism to optimize the electric field during erase and to minimize reliability problems and to minimize the degradation of erase speed.
2. Discussion of the Related Art
A microelectronic flash or block erase Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) includes an array of cells that can be independently programmed and read. The size of each cell and thereby the memory are decreased by omitting transistors known as select transistors that enable each cell to be erased independently. As a result, all of the cells must be erased together as a block.
A memory of this type includes individual Metal-Oxide-Semiconductor (MOS) field effect transistor memory cells, each of which includes a source, a drain, a floating gate and a control gate to which various voltages are applied to program the cell with a binary 1 or 0, or to erase all of the cells as a block.
The cells are connected in an array of rows and columns, with the control gates of the cells in a row being connected to a respective wordline and the drains of the cells in a column being connected to a respective bitline. The sources of the cells are connected together. This arrangement is known as a NOR memory configuration.
A cell is programmed by applying a voltage, typically about 9 volts to the control gate, applying a voltage of approximately 5 volts to the drain and grounding the source, which causes hot electrons to be injected from a drain depletion region into the floating gate. Upon removal of the programming voltages, the injected electrons are trapped in the floating gate and create a negative change therein which increases the threshold voltage of the cell to a value in excess of approximately 4 volts.
A cell is read by applying typically about 5 volts to the control gate, applying about 1 volt to the bitline to which the drain is connected, grounding the source, and sensing the bitline current. If the cell is programmed and the threshold voltage is relatively high (4 volts), the bitline current will be zero or at least relatively low. If the cell is not programmed or erased, the threshold voltage will be relatively low (2 volts), the control gate voltage will enhance the channel, and the bitline current will be relatively high.
A cell can be erased in several ways. In one arrangement, applying a relatively high voltage, typically 10-12 volts, to the source, grounding the control gate and allowing the drain to float erases a cell. This causes the electrons that were injected into the floating gate during programming to undergo Fowler-Nordheim tunneling from the floating gate through the thin tunnel oxide layer to the source. Applying a negative voltage on the order of minus 10 volts to the control gate, applying 5 volts to the source and allowing the drain to float can also erase a cell. Another method of erasing a cell is by applying 5V to the P-well and minus 10 volts to the control gate while allowing the source/drain to float.
A problem with the conventional flash EEPROM cell arrangement is that due to manufacturing tolerances, some cells become overerased before other cells are sufficiently erased. The floating gates of the overerased cells are depleted of electrons and become positively charged. This causes the overerased cells to function as depletion mode transistors that cannot be turned off by normal operating voltages applied to their control gates, and introduces leakage current during subsequent program and read operations.
More specifically, during program and read operations only one wordline that is connected to the control gates of a row of cells is held high at a time, while the other wordlines are grounded. However, a positive voltage is applied to the drains of all of the cells. If the threshold voltage of an unselected cell is very low, zero or negative, leakage current will flow through the source, channel and drain of the cell.
In a typical flash EEPROM, the drains of a large number, for example 512 transistor memory cells are connected to a bitline. If a substantial number of cells on the bitline are drawing background leakage current, the total leakage current on the bitline can exceed the cell read current. This makes it impossible to read the state of a cell on the bitline and renders the memory inoperative. The threshold voltages of the bits in an array typically form a voltage distribution with the least erased cells having a relatively high threshold voltage V
T
MAX whereas the most overerased cells have a minimum acceptable value V
T
MIN that can be zero or negative. The lower the threshold voltage and the wider the threshold voltage distribution the higher the leakage current. It is therefore desirable to prevent cells from being overerased and to reduce the threshold voltage distribution to as low a range as possible, with ideally all cells having the same high threshold voltage after erase on the order of 2 volts.
It is known in the art to reduce the threshold voltage distribution by performing an overerase correction operation that reprograms the most overerased cells to a higher threshold voltage. This operation will result in the threshold voltage distribution with all of the cells having a threshold voltage above a minimum acceptable value. An overerase correction operation of this type is generally known as Automatic Programming Disturb (APD).
An example of an APD method that is referred to as Automatic Programming Disturb Erase (APDE) is disclosed in U.S. Pat. No. 5,642,311, entitled “OVERERASE CORRECTION FOR FLASH MEMORY WHICH LIMITS OVERERASE AND PREVENTS ERASE VERIFY ERRORS,” issued Jun. 24, 1997 to Lee Cleveland. The method includes sensing for overerased cells and applying programming pulses thereto that bring their threshold voltages back up to acceptable values. Following application of an erase pulse, undererase correction is first performed on a cell-by-cell basis by rows. The cell in the first row and column position is addressed and erase verified by applying 4 volts to the control gate (wordline), 1 volt to the drain (bitline), grounding the source, and using sense amplifiers to sense the bitline current and thereby determine if the threshold voltage of the cell is above a value of, for example, 2 volts. If the cell is undererased (threshold voltage above 2 volts), the bitline current will be low. In this case, an erase pulse is applied to all of the cells and the first cell is erase verified again. After application of each erase pulse and prior to a subsequent erase verify operation, overerase correction is performed on all of the cells of the memory. Overerase verify is performed on the bitlines of the array in sequence. This is accomplished by grounding the wordlines, applying typically 1 volt to the first bitline and sensing the bitline current. If the current is above a predetermined value, this indicates that at least one of the cells connected to the bitline is overerased and is drawing leakage current. In this case, an overerase correction pulse is applied to the bitline. This is accomplished by applying approximately 5 volts to the bitline for a predetermined length of time such as 100 &mgr;s. After application of the overerase correction pulse the bitline is erase verified again. If the bitline current is still high indicating that one or more overerased cell still remains connected to the bitline, another overerase correction pulse is applied. This procedure is repeated for all of the bitlines in sequence. The procedure is repeated as many times as necessary until the bitline current is reduced to the predetermined value which is lower than the read current. Then, the procedure i
Cleveland Lee
Fastow Richard
Haddad Sameer S.
Sunkavalli Ravi S.
Thurgate Tim
Elms Richard
Nelson H. Donald
Nguyen Tuan T.
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