Feedback latch circuit and method therefor

Details Feedback latch circuit and method therefor Feedback latch circuit and method therefor

2003-08-27

2004-09-14

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S215000

Reexamination Certificate

active

06791387

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims priority of Taiwanese application No. 092109241, filed on Apr. 21, 2003.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a latch circuit, more particularly to a feedback latch circuit and latch method based on a modified Earle latch circuit design.
2. Description of the Related Art
Rapid progress in semiconductor manufacturing technology has made it possible to replace large and complex printed circuit board (PCB) based systems with semiconductor chip based systems. Particularly, it is now possible to integrate microprocessors, memories, analog circuits and radio frequency circuits into a single silicon chip. The size of the chip area is a factor that has a big influence on cost computations. In the design of very large scale integrated circuit (VLSI) chips, in order to ensure accuracy of input and output signals in a Boolean clock logic circuit, a latch circuit is usually coupled between input and output terminals of the chips. Accordingly, input and output signals can be latched so that normal operation of the clock circuit can be ensured. The design of a simple and fast latch circuit is a critical issue since it can affect both circuit layout and operating time.
As shown in
FIG. 1
, a conventional NAND-type static D-latch
2
requires both a true data input signal (DATA) and a complementary data input signal (DATA′) gated by a clock input signal (CLK). However, it is not easy to obtain the complementary data input signal (DATA′) for the D-latch
2
. Moreover, a three-level gate delay is incurred in the D-latch
2
.
A conventional Earle latch circuit
3
is shown in FIG.
2
. Unlike the D-latch
2
of
FIG. 1
, the Earle latch circuit
3
does not require a complementary data input signal (DATA′). Moreover, the complementary clock input signals (CLK, CLK′) can be easily obtained for the Earle latch circuit
3
. Furthermore, since there is only a two-level gate delay in the Earle latch circuit
3
, the Earle latch circuit
3
is faster than the D-latch
2
of FIG.
1
. When implemented in a two-level sum-of-product Boolean logic circuit, the Earle latch circuit
3
can reduce both delay and circuit area.
FIG. 3
illustrates a full-adder carry circuit
4
designed in accordance with the conventional Earle latch circuit
3
. The carry circuit
4
of
FIG. 3
requires three data inputs: a first addend (A), a second addend (B), and a carry (C). The logic equation of the carry circuit
4
is as follows:
Carry output (Cout)=(
A·B+A·C+B·C
)·CLK+(
A·B+A·C+B·C
) ·Cout+CLK′·Cout
where “+” stands for logic OR, and “·” stands for logic AND.
As evident from the foregoing, since the carry circuit
4
requires three data inputs (A, B, C), logic for the data inputs (A, B, C) must be duplicated for processing with the clock input signal (CLK) and the carry output (Cout), respectively. As a result, circuit area, power dissipation, and delay are inevitably increased.
SUMMARY OF THE INVENTION
Therefore, the object of the present invention is to provide a feedback latch circuit and latch method based on a modified Earle latch circuit design that can eliminate redundant logic in circuit applications to result in smaller circuit area, power dissipation and delay.
According to one aspect of the present invention, a feedback latch circuit comprises:
a first logic OR gate having a clock input terminal for receiving a clock input signal, a data input terminal, and an output terminal;
a first logic AND gate having a first data input terminal coupled to the output terminal of the first logic OR gate, a second data input terminal for receiving a data input signal, and an output terminal;
a second logic AND gate having a data input terminal coupled to the data input terminal of the first logic OR gate, a clock input terminal for receiving a complementary clock input signal that complements the clock input signal, and an output terminal; and
a second logic OR gate having a first data input terminal coupled to the output terminal of the first logic AND gate, a second data input terminal coupled to the output terminal of the second logic AND gate, and an output terminal coupled to the data input terminals of the first logic OR gate and the second logic AND gate.
A latch output of the feedback latch circuit is obtained from the output terminal of the second logic OR gate.
According to another aspect of the present invention, a latch-incorporating circuit comprises:
a set of first logic OR gates, each of which has a clock input terminal for receiving a clock input signal, a data input terminal, and an output terminal;
a set of first logic AND gates, each of which has a first data input terminal coupled to the output terminal of a respective one of the first logic OR gates, a number of data input terminals, each of which receives a data input signal, and an output terminal;
a second logic AND gate having a data input terminal coupled to the data input terminal of each of the first logic OR gates, a clock input terminal for receiving a complementary clock input signal that complements the clock input signal, and an output terminal; and
a second logic OR gate having a set of first data input terminals coupled respectively to the output terminals of the first logic AND gates, a second data input terminal coupled to the output terminal of the second logic AND gate, and an output terminal coupled to the data input terminals of the first logic OR gates and the second logic AND gate.
A data output signal of the latch-incorporating circuit is obtained from the output terminal of the second logic OR gate.
According to yet another aspect of the present invention, a latch-incorporating circuit comprises:
a first logic OR gate having a clock input terminal for receiving a clock input signal, a data input terminal, and an output terminal;
a set of first logic AND gates, each of which has a first data input terminal coupled to the output terminal of the first logic OR gate, a number of data input terminals, each of which receives a data input signal, and an output terminal;
a second logic AND gate having a data input terminal coupled to the data input terminal of the first logic OR gate, a clock input terminal for receiving a complementary clock input signal that complements the clock input signal, and an output terminal; and
a second logic OR gate having a set of first data input terminals coupled respectively to the output terminals of the first logic AND gates, a second data input terminal coupled to the output terminal of the second logic AND gate, and an output terminal coupled to the data input terminals of the first logic OR gate and the second logic AND gate.
A data output signal of the latch-incorporating circuit is obtained from the output terminal of the second logic OR gate.
According to still another aspect of the present invention, a feedback latch circuit comprises:
a first logic OR gate for performing a logic OR operation upon a clock input signal and a latch output;
a first logic AND gate, coupled to the first logic OR gate, for performing a logic AND operation upon output of the first logic OR gate and a data input signal;
a second logic AND gate for performing a logic AND operation upon a complementary clock input signal and the latch output, the complementary clock input signal complementing the clock input signal; and
a second logic OR gate, coupled to the first logic OR gate and the first and second logic AND gates, for performing a logic OR operation upon outputs of the first and second logic AND gates to result in the latch output that is provided to the first logic OR gate and the second logic AND gate.
According to a further aspect of the present invention, a latch method comprises:
performing a logic OR operation upon a clock input signal and a latch output to obtain a first logic OR output;
performing a logic AND operation upon the first logic OR output and a data input signal to obtain a first logic AND output;
performing a logic AN

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