Feedback-controlled substrate bias generator

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307304, H03L 100, H03K 3354

Patent

active

044396929

ABSTRACT:
A semiconductor circuit supplies a substrate back bias voltage that is feedback controlled as a function of the sum of the positive threshold voltage of one field-effect transistor (FET) and the negative threshold voltage of a second FET. Preferably, one of the FET's is an enhancement-mode device, and the other is a like-polarity depletion-mode device. This arrangement enables the bias voltage to vary from chip to chip in such a manner as to speed up the logic gates on a chip containing the slowest gates and to slow down the logic gates on a chip containing the fastest logic gates, thereby decreasing the chip-to-chip spread in gate propagation delay and average power dissipation. The worst-case noise margin increases slightly.

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patent: 4322675 (1982-03-01), Lee et al.
patent: 4336466 (1982-06-01), Sud et al.
patent: 4344003 (1982-08-01), Harmon et al.
patent: 4388537 (1983-06-01), Kanuma
Frantz, "Threshold Voltage Control for N-Channel MOSFET Devices", IBM Tech. Disl. Bull., vol. 12, No. 12, p. 2078, May 1970.
S. Chen et al., "Feedback Substrate Bias Generator", IBM Technical Disclosure Bulletin, vol. 23, No. 5, Oct. 1980, pp. 1930-1931.

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