Amplifiers – With semiconductor amplifying device – Including signal feedback means
Reexamination Certificate
2000-08-31
2003-01-07
Mottola, Steven J. (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including signal feedback means
C330S311000
Reexamination Certificate
active
06504435
ABSTRACT:
TECHNICAL FIELD
This invention relates generally to dual stage amplifiers, and more particularly to a dual stage amplifier with a clamp circuit for preventing overcharge in a compensation capacitor.
BACKGROUND OF THE INVENTION
Dual stage amplifier circuits are used in a variety of applications. Such circuits may include a differential input first amplifier stage with a second stage having an output related to the difference between the terminals of the first amplifier stage. A compensation capacitor is sometimes employed between the input and output of the second amplifier stage, in order to compensate for instability in the dual stage circuit. The size of such a compensation capacitor may be varied according to the desired frequency response characteristics of the circuit. Thus, where the bandwidth of the dual stage amplifier needs to be reduced, the compensation capacitor may be relatively large. For example, where a dual stage amplifier is used as an error amplifier in a switching regulator, it may be desirable to reduce the dual stage error amplifier bandwidth below the switching frequency of the switching regulator.
In addition to stability, the response time of the output may be an important performance characteristic of a dual stage amplifier. Where a compensation capacitor is employed between the input and output of the second amplifier stage, overcharging of the compensation capacitor may lead to unacceptably long output response times in the dual stage amplifier as well as undesirable overshoot in the output of a switching regulator or other closed loop system in which the dual stage amplifier is employed as an error amplifier. Such overcharging of the compensation capacitor may occur when the differential input terminals are imbalanced, such as during power up when the terminals are in indeterminate states. For example, in a switching regulator, a dual stage error amplifier may have a positive differential input terminal connected to a reference voltage source, and a negative differential input terminal connected to the regulated output through a resistive voltage divider network. Due to internal timing of the switching regulator, the reference voltage source may rise to its steady state voltage faster than does the regulated output. Thus, an imbalance occurs at the differential inputs, where the positive terminal is at the reference voltage and the negative terminal is near zero volts.
Such an imbalance at the dual stage amplifier inputs may cause the second stage input to go to one of the power supply rails or to ground in a single-ended configuration. Where the second amplifier stage is an inverter, such as a MOS transistor with a drain connected to the error amplifier output and a gate connected to the second stage input, the compensation capacitor may be connected in a feedback path between the drain and gate of the transistor. Excessive charging of the compensation capacitor may thus occur where an input imbalance condition causes the second stage input to go to ground or a supply rail. When the input imbalance condition is removed, the discharging of the compensation capacitor may lead to excessive dual stage amplifier output response time and/or closed loop system overshoot, particularly where the compensation capacitor is large. Accordingly, there exists a need for improved apparatus and methods by which dual stage amplifier output response time and system overshoot may be reduced or eliminated.
SUMMARY OF THE INVENTION
The present invention provides a dual stage amplifier with a clamping circuit and a methodology which minimize or overcome the above mentioned shortcomings, along with a clamping circuit for use with a dual stage amplifier. The invention may be employed in order to reduce the overcharging of a compensation capacitor in such a dual stage amplifier, however, the invention finds utility and may be advantageously employed in other applications.
According to one aspect of the present invention, there is provided a dual stage amplifier, comprising a first amplifier stage with a first input and a first output, a second amplifier stage having a second output and a second input operatively connected to the first stage output. The amplifier further includes a compensation capacitor in electrical communication with the second stage input and the second stage output, and a clamping circuit in electrical communication with the second stage, wherein the clamping circuit is adapted to prevent overcharging of the compensation capacitor. The clamping circuit may include a low vgs clamp, a high vgs clamp, and/or a combination low vgs and high vgs clamp, wherein the low vgs clamp is adapted to counteract a drop in the second stage input voltage, and the high vgs clamp is adapted to counteract a rise in the second stage input voltage.
According to another aspect of the invention, the low vgs clamp may sense a voltage drop at the second stage input and inject current from a positive supply into the second stage input to counteract the sensed voltage drop, whereby overcharging of the compensation capacitor is reduced. In this regard, the second amplifier stage may include a MOS output transistor with a gate operatively connected to the first stage output and a drain operatively connected to the second stage output, wherein the output transistor is adapted to control the second stage output according to the second stage input, for example, in an inverter amplifier configuration. In this case, the low vgs clamp may comprise a first switching component, such as an NMOS transistor, operatively connected to the gate of the output transistor and adapted to sense a voltage at the second stage input and to provide a signal according to the sensed voltage.
In addition, the low vgs clamp may include a second switching component, such as a PMOS transistor, operatively connected to the positive supply and the first switching component which selectively provides current to the gate of the output transistor according to the signal from the first switching component. In this manner, the current provided by the second switching device to the gate of the output transistor counteracts a voltage drop at the second stage input. Thus, in an inverter type second stage, the sourcing of current to counteract a drop in the second stage input effectively reduces the amount or likelihood of overcharging of a compensation capacitor operatively connected in a feedback path between the second stage input and the second stage output. The clamping circuit may be further adapted to activate the provision of current when the voltage at the second stage input has reached a certain trip point or value, allowing for normal amplifier operation above such a value. For example, the trip point on the low vgs clamp may be advantageously set above the threshold voltage of the second stage MOS transistor, in order to ensure operation of the clamp circuit prior to the second stage transistor shutting off.
Where the clamping circuit includes a high vgs clamp, alone or in combination with a low vgs clamp, the high vgs clamp may also prevent or minimize overcharging of the compensation capacitor. Toward this end, the clamp may be adapted to sense a voltage rise at the second stage input and to sink current to the negative supply from the second stage input to counteract the sensed voltage rise, whereby the possibility of overcharging the compensation capacitor is reduced.
For example, where the second amplifier stage comprises a MOS output transistor with a gate operatively connected to the first stage output and a drain operatively connected to the second stage output in an inverter configuration, the high vgs clamp may comprise a first switching component operatively connected to the gate of the output transistor and adapted to sense a voltage at the second stage input and to provide a signal according to the sensed voltage. A second switching component operatively connected to the negative supply and the first switching component then selectively sinks current from the gate of the output transistor accordi
Brady W. James
Mottola Steven J.
Swayze, Jr. W. Daniel
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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