Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Regenerating or restoring rectangular or pulse waveform
Patent
1996-12-16
1999-12-14
Callahan, Timothy P.
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Regenerating or restoring rectangular or pulse waveform
327149, 327158, 375359, H03K 513, H03K 1728
Patent
active
060022825
ABSTRACT:
A closed loop clock delay adjustment system measures the drift between the delay introduced by clock buffers and by delays inserted at the device data input pins. The system uses a reference delay at the input of a measurement flip-flop. The reference delay is defined to be an approximate average of the delays at the data input pins. An external clock signal is coupled to the input of the reference delay. The output of the reference delay is coupled to the data input of the measurement flip-flop. The external clock signal is also coupled to the input of a variable clock delay buffer sub-circuit. The output of the variable clock delay buffer is coupled to the clock signal input of the measurement flip-flop. In operation, the measurement flip-flop compares the variable clock delay buffer output signal with the clock signal delayed by the reference delay. If the variable clock delay buffer output signal is delayed more than the reference delay output signal, the variable clock delay is decreased. If the variable clock delay buffer output signal is delayed less than the reference delay output signal, the variable clock delay is increased. The input of an up-down counter is coupled to the measurement flip-flop output. The digital output of the up-down counter is converted to an analog signal which then controls the variable clock delay buffer. This closed loop clock delay adjustment system maintains the clock delay within a small range of a predetermined optimal value.
REFERENCES:
patent: 4316150 (1982-02-01), Crosby
patent: 4637018 (1987-01-01), Flora et al.
patent: 4682116 (1987-07-01), Wolaver et al.
patent: 5101117 (1992-03-01), Johnson et al.
patent: 5164677 (1992-11-01), Hawkins et al.
patent: 5216302 (1993-06-01), Tanizawa
patent: 5223755 (1993-06-01), Richley
patent: 5266851 (1993-11-01), Nukui
patent: 5455540 (1995-10-01), Williams
patent: 5486783 (1996-01-01), Baumert et al.
patent: 5514990 (1996-05-01), Mukaine et al.
patent: 5670903 (1997-09-01), Mizuno
Xilinx, Inc., "The Programmable Logic Data Book," Sep. 1996, pp. 13-45, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124.
Callahan Timothy P.
Hoffman, Esq E. Eric
Shin Eunja
Xilinx , Inc.
Young Edel M.
LandOfFree
Feedback apparatus for adjusting clock delay does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Feedback apparatus for adjusting clock delay, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Feedback apparatus for adjusting clock delay will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-866966