Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2003-01-30
2004-06-29
Guerrero, Maria (Department: 2822)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S014000, C438S624000, C438S626000, C438S631000, C438S633000, C438S637000
Reexamination Certificate
active
06756309
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to chemical mechanical polishing (CMP) and more particularly to a method for dynamically adjusting a CMP process according to predetermined previous measurements of layer and feature dimensions in a feed-forward process to achieve a targeted metal line electrical resistance (Rs).
BACKGROUND OF THE INVENTION
In semiconductor fabrication integrated circuits and semiconducting devices are formed by sequentially forming semiconductor device features (structures) in sequential layers of material in a bottom-up manufacturing method. In order to form reliable devices, close tolerances are required in forming features, for example metal lines to achieve precise control of the electrical resistance, frequently measured as a sheet resistance (Rs), of the various metal lines.
For example, prior art processes rely on CMP planarization methods for determining a final metal line thickness. For example, in a damascene metallization process, one or more dielectric insulating layers are formed followed by anisotropic etching to form a trench opening in the dielectric insulating layer. Following formation of the trench, metal is deposited to fill the trench opening which is followed by a CMP process to planarize the upper surface of the process wafer and to define the final dimension of the metal line.
In the formation of metal lines, also referred to as conductive interconnections, copper is increasingly used for forming metal interconnects such as vias and trench lines since copper has low resistivity and good electromigration resistance compared to other traditional interconnect metals such as aluminum. The undesirable contribution to electrical parasitic effects by metal interconnect resistivity has become increasingly important as device sizes have decreased. As device sizes decrease even further, it is becoming more important to precisely control the width and depth of the metal lines in order to precisely control the resistance of the metal lines.
In prior art processes, the determination of the final thickness of the metal lines, for example copper metal lines, is determined following a copper CMP process where an excess of copper deposited to fill the trench opening is removed from the overlying surface. In prior art processes, deviations originating in processes prior to CMP and contributing to the final depth of the metal lines is not taken into account in formulating subsequent processes such as CMP. For example copper CMP typically relies on polishing times determined from expected results based on previous model processes. Following the CMP process the thickness of the metal layer is determined which in part determines a sheet resistance. If prior process deviations unexpectedly contribute to a less than desirable metal line thickness (resistance), there is little that can be done to correct the problem especially if the CMP process has removed an excessive amount of the metal line.
Therefore, there is a need in the semiconductor art to develop an improved method for achieving improved metal line electrical resistance precision including a CMP polishing process.
It is therefore an object of the invention to provide an improved method for achieving improved metal line electrical resistance precision including a CMP polishing process while overcoming other shortcomings and deficiencies in the prior art.
SUMMARY OF THE INVENTION
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for achieving a predetermined electrical resistance of a semiconductor device metal line in a CMP process.
In a first embodiment, the method includes providing a semiconductor process wafer comprising at least one dielectric layer for etching an opening through a thickness of the at least one dielectric layer; measuring a thickness of the at least one dielectric layer prior to etching the opening; etching the opening through a thickness of the at least one dielectric layer; measuring at least one dimension of the opening from which at least an opening depth is determined; forming a metal layer to fill the opening; and, performing a chemical mechanical polish (CMP) process to remove at least the metal layer overlying the opening level to form a metal filled opening according to a projected metal filled opening electrical resistance.
These and other embodiments, aspects and features of the invention will be better understood from a detailed description of the preferred embodiments of the invention which are further described below in conjunction with the accompanying Figures.
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Sakai et al. “Development of a novel air-back wafer carrier with an integrated end-point detector for copper CMP application”, Jun. 1999, IEEE, pp. 183-186.
Chen Chii-Ping
Chien Wen-Chen
Tsai Ching-Ming
Guerrero Maria
Taiwan Semiconductor Manufacturing Co. Ltd
Tung & Associates
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