Radiant energy – Irradiation of objects or material – Irradiation of semiconductor devices
Reexamination Certificate
2000-01-19
2003-07-01
Pert, Evan (Department: 2829)
Radiant energy
Irradiation of objects or material
Irradiation of semiconductor devices
C250S492230, C438S005000, C438S007000
Reexamination Certificate
active
06586755
ABSTRACT:
BACKGROUND
1. Field of Invention
The invention is generally directed to the mass production of semiconductor devices. The invention is more specifically directed to the problem of tightening statistical variation of critical performance parameters during mass production of semiconductor devices, where the fabrication process includes TCI (Tilted Channel Implant) doping.
2a. Cross Reference to Issued Patents
The disclosures of the following U.S. patents are incorporated herein by reference:
(A) U.S. Pat. No. 5,926,690 issued Jul., 20, 1999 to Toprac, et al, and entitled, Run-to-run Control Process for Controlling Critical Dimensions; and
(B) U.S. Pat. No. 5,863,824 issued Jan. 26, 1999 to Gardner, et al, and entitled, Method of Forming Semiconductor Devices Using Gate Electrode Length and Spacer Width for Controlling Drive Current Strength.
2b. Description of Related Art
A mass-production tolerance problem emerges as the historically-consistent, and industry-pervasive, shrinkage for the effective length (L
eff
) of transistor channels continues on to smaller and smaller dimensions. Statistical variations tend to crop up over time in the mass-production processes that ultimately define effective channel length (L
eff
). Of importance, such statistical variations show up in what may termed as critical dimensions (CD's) of in-process structures.
More specifically, it is predicted that shrinkage of dimensions will continue as it had in the past, with the implementation of ever smaller dimensions of channel length, such as moving from devices with channel lengths of about 0.25&mgr; (0.25 micron) or less, down to devices with channel lengths of about 0.18&mgr; or less, and then continuing down to devices with channel lengths of about 0.09&mgr; or less, and perhaps continuing to even substantially smaller dimensions. As these dimensions shrink, the so-called ‘critical dimensions’ (CD's) of transistor-precursor structures (which structures appear during mass-production) become more and more difficult to control with precision. At the same time, the mass-production replication of such CD's becomes more significant to final device performance as channel length dimensions shrink. New methods are needed for providing tighter process control of critical performance parameters so that desired statistical mean and 3 sigma (3&sgr;) values can be obtained for mass-produced devices.
One factor that can play a substantial role in determining the ultimate L
eff
of each individual one of mass-produced transistors is the precision with which the actual length of the patterned gate material (e.g., polysilicon) can be controlled. This patterned gate material is that which remains in the transistor-precursor structure after completion of mass-production photomasking, mass-production resist trimming, and mass-production gate-material etch.
Another factor that can play a role in determining the ultimate L
eff
, in cases where sidewall spacers are formed and trimmed about the post-etch gate, is the precision to which the deposition and trimming of such sidewalls is carried out.
The interplay between such factors will become more apparent when the drawings are described in detail below. For now, it is sufficient to understand how, in a conventional fabrication process, an ideal or target value (L
GateT
) is established for the final length of the gate material that remains after gate-layer etching. Due to statistical process variations, and even though the measured, actual gate length (the gate FICD) will tend to have an average or mean value that is close to the ideal or target value (L
GateT
), individually-sampled dice or wafers or lots will tend to exhibit gate FICD's (Final Inspection measurements of Critical Dimension) that deviate by finite amounts from the target value. In other words, there will typically be a manufacturing tolerance error that may be expressed as:
e
Gate
=L
GateT
−FICD
{Eq. 1}.
The group of fabrication technicians and/or other personnel who are responsible for keeping the post-etch gate length (as measured by FICD) close to the established ideal or target value (L
GateT
), will typically define an allowed tolerance-range, e
1
≦e
Gate
≦e
2
(where e
1
is typically less than zero while e
2
is greater than zero). Nonconforming, post-etch wafers will usually be thrown away.
If, at a given time during production, a statistically significant number of FICD measurements begin to fall outside the predefined, allowed tolerance-range, e
1
≦e
Gate
≦e
2
, then production might need to be temporarily halted to find out why there is an such an unusual increase in the number of nonconforming, post-etch wafers. Specialty personnel (e.g., gate-etch control engineers) may have to be called in to determine what, if any, fine tunings should be made to the gate-etch process to bring its statistical results (mean and 3&sgr; deviation) back to acceptable numbers.
This is risky business. Sometimes an observed set of extreme deviations is just a random coincidence and the correct response (as can be shown only by hindsight) is to leave the gate-etch process unchanged. If a fine-tuning is nonetheless applied, that tuning may itself, over time, cause an even larger number of wafers to fall outside the allowed tolerance-range, e
1
≦e
Gate
≦e
2
.
Further downstream along the mass-production line, there may be a second group of fabrication personnel who are responsible for applying (depositing) and trimming down, gate sidewalls. This second group will face a similar dilemma. They will establish statistical mean and allowed deviation ranges for sidewall film thickness and trim-down distance. The allowed range may be expressed as, e
3
≦e
Sidewall
≦e
4
, where e
Sidewall
is the error between measured and target thickness dimensions for the gate sidewalls, and e
3
is typically less than zero while e
4
is greater than zero. Nonconforming, post-trim wafers may have to be thrown away or stripped and re-worked.
If a statistically significant number of sidewall-thickness measurements begin to come back as falling outside the allowed tolerance-range, e
3
≦e
Sidewall
≦e
4
, then production might need to be temporarily halted. Specialty personnel (e.g., sidewall-deposition and trim control engineers) may have to be called in to determine what, if any, fine tunings should be made to the sidewall-deposition and/or sidewall-trim processes to bring their statistical results (mean and 3&sgr; deviation) back to acceptable numbers. Like the case involving fine tuning of the gate-etch process, fine tuning of the sidewall-deposition and/or sidewall-trim processes is risky business. Sometimes an observed set of extreme deviations is just a random coincidence and the correct response is to leave the sidewall-related processes unchanged. If a fine-tuning is nonetheless applied, that tuning may over time, push an even larger number of samples outside the allowed tolerance-range.
It is seen from the above that CD measurement practices and statistical analysis and response practices can produce dilemmas. On the one hand, semiconductor manufacturers want to obtain good yield of final product in as little time as possible. On the same hand, they want to avoid the costs of human intervention. On the other hand, they want to avoid the possible errors of human judgment that might come to play with constant, manually-determined fine tunings to each gate etch or sidewall deposition or sidewall trim process. To achieve the end result of avoiding judgment errors, it has been generally accepted that the gate FICD's (measured critical dimensions) must be maintained within very tight tolerances, even if that goal leads to a throwing away of large numbers of post-etch wafers. But that means that yield suffers. It is a situation that leaves practitioners in a can't-win dilemma. They can suffer yield loss by taking either choice, namely, (a) throwing away large numbers of wafers and not re-tuning the production line, or (b) re-tuning the production l
Heavlin William D.
Krivokapic Zoran
Advanced Micro Devices , Inc.
Fliesler Dubb Meyer & Lovejoy LLP
Pert Evan
LandOfFree
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