Feed-forward approach for timing skew in interleaved and...

Details Feed-forward approach for timing skew in interleaved and... Feed-forward approach for timing skew in interleaved and...

2002-03-25

2003-05-27

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S095000, C327S096000, C327S337000

Reexamination Certificate

active

06570410

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the field of integrated circuits, and more particularly to a system and method of generating timing signals in interleaved and/or double-sample circuits to eliminate timing skew or timing mismatch errors associated therewith.
BACKGROUND OF THE INVENTION
Analog to digital converters (ADCs) are important analog circuit devices which take an analog input signal and generate one or more digital signals which are representative of the analog input. ADCs are used in many applications such as communications applications in which the components receive a voice input (an analog input) and transform the voice data into a digital format for subsequent processing.
In many telecommunication applications, high-speed, high-resolution ADCs are needed. High resolutions of 14 bits or greater have been achieved using over-sampling sigma-delta converters and pipelined converters, but the signal bandwidth is typically limited to a few megahertz (MHz). By using time-interleaved ADCs, high sampling rates can be achieved. Note that in prior art
FIG. 1
, a traditional non-interleaved ADC system
10
is illustrated. In the ADC system
10
, an analog input signal
12
is sampled by the ADC at a sampling frequency f
S
to provide a digital type output
14
. Note, however, that the ADC system
10
is limited by how fast the circuitry therein can operate. Therefore the sampling frequency f
S
is limited, thereby limiting the conversion rate thereof.
Turning now to prior art
FIG. 2
, the conversion rate of an ADC system
20
is increased substantially by a time-interleaving technique, wherein several ADCs,
22
,
24
and
26
operate in parallel using different clock phases
27
,
28
and
29
, respectively. This time-interleaving technique enables a higher conversion speed since each of the individual ADCs
22
,
24
and
26
need only operate at a sampling rate f
S
/N, wherein N is an integer representing the number of parallel-operating ADCs. Each of the digital outputs
30
from the ADCs
22
,
24
and
26
are then brought together to form a digital output
32
via a multiplexer
34
, as illustrated. Thus the system
20
provides a total sampling frequency of f
S
, while each of the individual ADCs need only operate at f
S
/N. Thus the total sampling frequency f
S
may be increased.
The performance of the time-interleaved converter system
20
of prior art
FIG. 2
is limited by the accuracy of each channel ADC
22
,
24
and
26
; however, there are additional errors that may arise in the sampled output
32
which are caused by mismatch between the channels. The three chief types of mismatch associated with time-interleaved converters are offset mismatch, gain mismatch and timing mismatch (which is often referred to as phase skew error). The offset and gain mismatch errors are relatively easy to resolve, for example, via calibration in either the analog or digital domain. Phase skew errors, however, are not easily calibrated, since dynamic input signals are required to measure the delay skews. Furthermore, even a small phase skew of as little as 25 ps may limit the input frequency of a 10-bit converter to less than 10 MHz.
Due to the difficulties in calibrating delay skews, a passive sampling technique has been employed in conventional circuits. For example, as illustrated in
FIG. 3
, an ADC system
40
employs passive sampling circuits such as sample and hold circuits
42
,
44
and
46
in series with each of the sub-ADCs
22
,
24
and
26
, respectively. Each of the sample and hold circuits
42
,
44
and
46
are operable to sample the analog input
12
based on their unique clock phase (&phgr;
1
, &phgr;
2
, . . . &phgr;
N
). Although the solution
40
of prior art
FIG. 3
does reduce phase skew error, such phase skew error or timing mismatch is not fully eliminated; instead such error still exists when the N different clock phases themselves are generated to drive the sample and hold circuits
42
,
44
and
46
. Even small differences in delay between the various clock phases may generate substantial distortion at high signal frequencies.
The sample and hold circuits
42
,
44
and
46
discussed above in conjunction with the exemplary system of prior art
FIG. 2
are single sample type circuits, in which a single sample of the analog input is taken for each clock cycle of its respective sampling clock (e.g., &phgr;
1
for circuit
42
). In order to further improve the sampling speed of sample and hold circuits, a double-sampling type sample and hold circuit has been developed, as illustrated in prior art FIG.
4
and designated at reference numeral
50
. The circuit
50
uses both the rising edge and falling edge of a sampling clock (and thus generally opposite or complimentary phases &phgr;
1
and &phgr;
2
) to efficiently utilize an op-amp
52
associated therewith. For example, when &phgr;
1
is high, the analog input
12
is sampled on C
1
, while C
2
is holding a previous sample via a feedback connection of the op-amp
52
. Similarly, when &phgr;
2
goes high and &phgr;
1
goes low, the input
12
is sampled on C
2
while the sample previously associated with C
1
is held via the op-amp feedback configuration.
Note, however, that two additional signals &phgr;
1P
and &phgr;
2P
drive respective switches
54
that selectively couple the second terminal of the capacitors C
1
and C
2
, respectively, to circuit ground. These signals are pre-phase signals and initiate the sample instant when their signals go low, such that the respective capacitor is decoupled from ground. Shortly thereafter, the corresponding switch
56
connected to the input
12
is turned off, and the respective switches
58
and
60
are turned on, thus connecting the respective sampling capacitor into the feedback loop. This technique is referred to as bottom plate sampling and aids in avoiding signal dependent errors which may otherwise occur if the sample had been taken by first closing the switches
56
between the capacitors C
1
and C
2
and the input
12
.
As can be seen from the above, the double-sampled circuit
50
has two parallel signal paths and timing mismatch therebetween may introduce some errors at the output. For example, timing skew in the clock signals for the parallel channels leads to non-uniform sampling. Such timing skew may result from unmatched propagation delays from a clock generator circuit to the switches or may originate within the clock generator itself. One exemplary prior art clock signal generator is illustrated in prior art
FIGS. 5 and 6
, and is designated at reference numeral
70
. As illustrated in
FIG. 5
, the clock generator circuit
70
is operable to take a single input clock signal CLK and generate four phase signals &phgr;
1
, &phgr;
1P
, &phgr;
2
and &phgr;
2P
associated therewith.
As illustrated in prior art
FIG. 6
, an input clock signal &phgr;
72
and its compliment &phgr;
Z
74
each drive parallel signal paths which employ a cross-coupled feedback feature via signals
75
and
76
, as illustrated. In the clock generator circuit
70
of prior art
FIG. 6
, the pre-phase signals &phgr;
1P
and &phgr;
2P
are a function of the cross-coupled feedback loops and have differing pulse widths, as illustrated in the timing diagram of FIG.
7
. Therefore the falling edge
78
of &phgr;
1P
and the falling edge
79
of &phgr;
2P
are skewed with respect to an ideal sampling clock, running at twice their frequency, and defining the sampling times for the input signal
12
of FIG.
3
. This difference causes a systematic periodic sampling pattern, which results in a phase modulation of the input samples and thus leads to harmonic distortion on the output of the double-sample circuit
50
of prior art FIG.
4
.
One conventional solution to the above problem is illustrated in prior art
FIG. 8
, wherein a double-sampled sample and hold circuit
80
is provided. The circuit
80
is similar to the circuit
50
of prior art
FIG. 4
, except that the switches
54
are no longer driven by pre-phase signals &phgr;

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