Feature-based defect detection

Image analysis – Applications – Manufacturing or product inspection

Reexamination Certificate

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C382S286000

Reexamination Certificate

active

06539106

ABSTRACT:

COMPUTER PROGRAM LISTING APPENDIX
This disclosure incorporates by reference a computer program listing appendix on compact disk and having 1 disk and one duplicate disk and each disk having the following files: M-7229-1, having Appendices A to G; the assignee of this application reserves all copyright rights on the content of this computer program listing.
COPYRIGHT NOTICE
A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by any one of the patent disclosure, as it appears in the Patent and Trademark office patent files or records, but otherwise reserves all copyright rights whatsoever. 37 CFR §1.71.
BACKGROUND
1. Field of the Invention
The invention relates to the detection of defects in patterned substrates, such as semiconductor wafers, particularly based on features in voltage-contrast images.
2. The Prior Art
Manufacture of semiconductor devices involves many process steps resulting in patterns on a substrate. If the patterns of an intermediate stage of production are defective, they can result in defective die and, thus, low yields. Methods and apparatus for inspecting the patterns on semiconductor wafers at intermediate stages of production (“in-process”) are known. These include systems and methods based on identification of pattern defects visible in optical images of the wafer. At least one approach is based on voltage-contrast images of the wafer acquired using a scanning electron beam, as described in U.S. Pat. Nos. 5,502,306 and 5,578,821 and implemented in the SEMSpec system offered commercially by KLA-Tencor Corp.
A prior method for detecting defects from voltage-contrast images is based on differencing of pixel-intensity values, pixel-by-pixel, between an image of the pattern to be inspected and a reference image. In this method, two voltage-contrast images, or two regions of one voltage-contrast image, are compared. To extract defects, the two images or image regions are first corrected for differences in brightness and contrast and aligned with one another. Then the difference of pixel-intensity values is taken, pixel-by-pixel, to produce a difference image. The resulting difference image is thresholded to produce a defect image in which the pixel values are binary. Features in the defect image meeting certain conditions, such as minimum size, shape, intensity, etc., are considered defects. Statistics of the defects in the images are then computed and reported. For example, the largest defect and total number of defects might be returned for each image. Then the images are reviewed based upon these statistics so that the most significant defects are processed and analyzed first, thereby reducing the review time considerably.
A strength of this method is that it requires little knowledge of electrical features or structures in the voltage-contrast images, only that they are of the same approximate size in both images or image regions and that alignment and image normalization will correct the overall differences in the images or image regions. This method allows voltage-contrast defects to be detected without first knowing what electrical patterns are being inspected.
But this strength is also a weakness: all image differences are considered potential defects even if they are not, so it is not possible to differentiate “killer” defects from “nuisance” defects or “false” defects. A “killer” defect is a defect of electrical significance in final test of a die, leading to reduced reliability or reduced electrical performance. A “false” defect is a report from a defect detection system of a defect which does not correspond to any surface or image artifact, resulting for example from an error by the defect system. A “nuisance” defect is a surface or image artifact which is real but is not a killer defect or otherwise of interest. Some artifacts of the inspection process are due to image misalignment, local image distortions and non-linearities of the scanning process used to acquire the voltage-contrast images. Since the occurrence of killer defects is in general quite rare, the number of nuisance defects detected can be much larger than the number of killer defects. In conventional, pixel-based inspection systems, 90% or more of the reported defects can be nuisance defects. Separating these from the killer defects requires time-consuming and costly human review and judgment. The high rate of nuisance defects and false defects and need for human intervention make it difficult to improve the performance of the inspection process to make it more useful in semiconductor wafer fabrication. Existing solutions to reduce the rate of nuisance defects and false defects caused by misalignment, such as precise wafer-stage positioning, more uniform and repeatable imaging, and improved defect-detection algorithms, do not eliminate the problem and typically reduce sensitivity to killer defects. At the same time, these solutions require more processing, and thus more processing time or more processing hardware. This limits throughput and the performance vs. price ratio.
Another drawback is that, since the method is pixel-based, it can only detect differences of intensity pixel-by-pixel. This makes detection of certain types of defects difficult if not impossible. Co-pending U.S. patent application Ser. No. 09/226,962 describes techniques for enhancing the visibility in a voltage-contrast image of electrically-significant defects in features such as unfilled contact holes. These techniques cause a change in the apparent size of the unfilled contact hole in the voltage-contrast image depending on electrical connectivity of material in the contact hole. While a pixel-based image-comparison method might detect the change in size as an intensity difference for pixels surrounding the contact hole, and pixel-intensity differencing might show a doughnut-shaped defect, it would not reveal the fundamental manifestation of this type of defect—an apparent change of size of the feature rather than a change of intensity.
FIG. 1
shows a prior method in which images are acquired and processed in parallel. The image acquisition portion begins with setup of a batch file at step
105
, followed by image acquisition at step
110
, storage of the image at step
115
, and moving to a next image at step
120
. Images are stored in a disk storage device
125
. Steps
110
,
115
and
120
are repeated for other regions of a wafer and, when imaging of the wafer is complete, imaging of another wafer begins. Once an image has been acquired, image processing proceeds in parallel with acquisition of further images. Image processing begins with alignment of the acquired image with a reference image at step
130
, then the pixel-intensity levels of the images are differenced at step
135
to produce a difference image. Noise is reduced from the difference image at step
140
, followed by counting of features in the difference image at step
145
. Features in the difference image are sorted at step
150
, and manually reviewed at step
155
to decide which of the features are to be considered defects.
Methods and apparatus are desired which will offer a lower rate of nuisance defects and less need for human intervention, and thus improved throughput and performance vs. cost.
SUMMARY
Methods and apparatus consistent with the invention employ feature-based image processing to detect, quantify and analyze defects in inspection of patterned substrates, such as semiconductor wafers, from voltage contrast e-beam images. A method of inspecting a patterned substrate comprises: preparing a reference image and a test image, extracting features from the reference image and extracting features from the test image, matching features of the reference image and features of the test image, and comparing features of the reference image and of the test image to identify defects. The images can be aligned before matching features. The reference image can be a voltage-contrast image of a first patterned

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