Feasible, gas-dielectric interconnect process

Details Feasible, gas-dielectric interconnect process Feasible, gas-dielectric interconnect process

1996-08-15

2001-10-23

Everhart, Caridad (Department: 2825)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S522000, C438S624000, C438S619000

Reexamination Certificate

active

06307265

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a special interconnection insulating structure and also to a method of manufacturing the semiconductor device.
2. Description of the Related Art
Improvement of an LSI (Large Scale Integrated Circuit) essentially resides in an increase in the density at which elements are packed in the LSI, namely in a decrease in the size of the elements. If the packing density of elements is increased, however, the inter-wire capacitance will increase. The greater the inter-wire capacitance, the more difficult it will be to enhance the performance of the LSI (e.g., the operating speed).
To enhance the performance of an ultra-large scale integrated circuit (ULSIC) such as a microprocessor, it is absolutely necessary to reduce the parasitic resistance and parasitic capacitance of the wires used in the ULSIC. The parasitic resistance of the wires can be decreased by using a low-resistivity material for the wires. At present, it is proposed that the wires be made of copper, instead of aluminum alloy. This is because the resistivity of copper is 30% or more lower than that of aluminum alloy.
The parasitic capacitance of the wires has two components. The first component is the capacitance among wires located at different levels. This capacitance can be reduced by increasing the thickness of the inter-layer insulating films used. The second component is the capacitance among wires located at the same level. This capacitance can be reduced by increasing the space between the wires and by decreasing the thickness of the wires.
To increase the space between the wires is to lower the packing density of elements, and to decrease the thickness of the wires is to increase the resistance of the wires. Hence, if the wires are spaced farther apart and made thicker, the performance of the LSI can no longer be enhanced. In order to reduce the parasitic capacitance among the wires, it is proposed that the insulating layers interposed between the wires be made of material having a small dielectric constant &egr;.
FIG. 233
shows a semiconductor device in which insulating layers having a small dielectric constant are interposed between the wires. AS shown in
FIG. 233
, an insulating layer
12
is provided on a semiconductor substrate
11
. Lines
13
are formed on the insulating layer
12
. Formed on the layer
12
and on the wires
13
is a plasma TEOS layer
14
which contains fluorine. The plasma TEOS layer
14
containing fluorine has a dielectric constant &egr; of about 3.3, which is about 15% less than the dielectric constant of plasma TEOS which does not contain fluorine.
As the packing density of elements has been increasing steadily, the performance of LSIs cannot be enhanced unless the inter-wire insulating layers have a dielectric constant &egr; of less than 3.3. Thus, the dielectric constant of inter-wire insulating layers must be decreased by any means to improve the performance of LSIs. It is, however, extremely difficult to reduce the constant to a value less than 3.3. The inter-wire insulating layers used at present, which has a dielectric constant of 3.3 or more, is a bar to the improvement of LSIs in terms of their performance.
In recent years, an attempt has been made to void the spaces between the wires arranged at the same level so as to reduce the parasitic capacitance among these wires. This technique is disclosed in, for example, Jpn. Pat. Appln. KOKAI Publication 7-45701. More specifically, water is filled in the inter-wire spaces, cooled to solidify, turning into ice layers, and the ice layers are evaporated, rendering the spaces void.
This technique is disadvantageous in three respects because a change in phase of the material is utilized. First, the water filled in the inter-wire spaces adversely influences the wires as it solidifies and expands. This holds true of any other material that is disclosed in the above-identified publication and that can be used in place of water. Second, the ice layers in the inter-wire spaces may melt away in some cases, due to the heat generated as they are polished by CMP (Chemical Mechanical Polishing). Third, the wafer must be cooled to a low temperature (below 0° C. when water is used) until the ice layers are evaporated. This inevitably makes it difficult to handle the semiconductor wafer.
Moreover, the water vapor which fills the inter-wire spaces for some time after the ice layers have been evaporated may cause short-circuiting of the wires or corrosion of the wires, or both. The water vapor may therefore impair the reliability of the wires.
Further, this technique cannot make void the spaces between wires which are arranged at different levels. Therefore, it does not serve to reduce the parasitic capacitance among all wires, including those located at the same level, as much as is desired.
SUMMARY OF THE INVENTION
The present invention has been made to solve the problems described above. Its object is to provide an LSI which has an increased packing density of elements and an enhanced performance.
According to a first aspect of this invention there is provided a semiconductor device which comprises: a semiconductor substrate; a first insulating layer provided on the semiconductor substrate; wires of a first set provided on the first insulating layer; a second insulating layer having via holes and formed on the wires of the first set, providing complete cavities between the wires of the first set; wires of a second set provided on the second insulating layer; conductors of a first set filled in the via holes of the second insulating layer and connecting the wires of the first set to the wires of the second set; and a third insulating layer provided on the wires of the second set, providing complete cavities among the wires of the second set.
The cavities provided among the wires of the first set and the cavities provided among the wires of the second set are filled with either air or a mixture gas consisting of at least oxygen and carbon dioxide.
The first insulating layer has a flat surface.
According to a second aspect of the invention there is provided a method of manufacturing a semiconductor device, which comprises the steps of: forming a first insulating layer on a semiconductor substrate; forming a solid layer on the first insulating layer; forming slits in the solid layer; forming conductors in the slits of the solid layer, thereby forming wires; forming a second insulating layer on the solid layer and the wires; and oxidizing the solid layer, changing the same into gas layers.
The solid layer is a carbon layer. The carbon layer is ashed, thereby providing complete cavities among the wires, which are filled with a mixture gas consisting of at least oxygen and oxygen dioxide.
The solid layer is made of material which remains solid at a temperature equal to or lower than a temperature at which the conductors are formed, and which can be processed to have slits, and which can easily change into gas when oxidized.
The slits are formed by a series of steps of: forming a mask layer on the solid layer; performing photo engraving process on the mask layer; performing anisotropic etching on the solid layer, while using the mask layer as a mask; and removing the mask layer.
The mask layer is formed by sputtering if it is made of oxide.
The slits are formed by a series of steps of: forming a resist on the solid layer, patterning the resist, performing anisotropic etching on the solid layer, while using the resist as a mask; and removing the resist. The resist is removed by applying a solution of H
2
SO
4
and H
2
O
2
.
The second insulating layer is formed by sputtering if it is made of oxide.
The solid layer is oxidized by heat treatment in an oxygen atmosphere or by treatment in O
2
-plasma.
The gas layer can be layers of air.
According to a third embodiment of the present invention, there is provided a semi-conductor device which comprises: a semiconductor substrate having a surface region; a semiconductor element provided in the s

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