FDDI network test adaptor error injection circuit

Details FDDI network test adaptor error injection circuit FDDI network test adaptor error injection circuit

1992-04-30

1994-11-08

Beausoliel, Jr., Robert W.

Excavating

G06F 1100

Patent

active

053633792

ABSTRACT:
An apparatus for injecting errors into a FDDI token ring network is disclosed. The error injection scheme operates by fooling a FORMAC into thinking it sent a real frame of data. This is done by using two RAM buffers. The RAM buffer normally accessed by the RBC/DPC becomes a SHADOW RAM during error injection operation. A dummy frame is loaded into the shadow RAM in order to fool the FORMAC. This data is just like the data that would be used if sending a normal frame, with the restriction that it must be shorter than the error injection data. The other buffer, the error injection RAM, contains the error injection frame. The error injection data is sent out to the media by switching a multiplexor. When the FORMAC is done transmitting the data, the multiplexor is switched back to the normal mode. Thus, the FORMAC is unaware of what happened and the token ring remains operational.

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patent: 4866704 (1989-09-01), Bergman
patent: 4979167 (1990-12-01), McCool
patent: 5121396 (1992-06-01), Irvin et al.
patent: 5168496 (1992-12-01), Ohba et al.
patent: 5233603 (1993-08-01), Takeuchi et al.

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