FDDI bit error rate tester

Details FDDI bit error rate tester FDDI bit error rate tester

1988-03-25

1991-06-11

Smith, Jerry

Excavating

371 206, G06F 1100

Patent

active

050238728

ABSTRACT:
Methods and apparatus are set forth which facilitate continuous bit error rate monitoring at the physical (PHY) management layer in a Fiber Distributed Data Interface (FDDI), duel token ring network. The monitoring is performed using existing line status information from PHY. Simple error detection logic. In combination with an error counter and a timer, is used to detect errors during active or idle line state conditions, independent of Media Access Control (MAC) layer support.

REFERENCES:
Joshi, "High Performance Networks: A focus on the Distributed Data Interface (FDDI) Standard", IEEE Micro, 06/1986, pp. 8-14.
Moor et al., "FDDI: A Federal Government LAN Solution", Telecommunications, vol. 23, No. 9, 9/1989.
Kajos et al., "FDDI Link Error Rate Monitor", 14th Conference on Local Computer Networks, Minneapolis, MN, Conference Date, 10/1989 (abstract only).
Figueroa, "Single Chip Implements FDDI Physical Layer: CMOS Part Consumer Less than 800MW", EDN, vol. 35, No. 13A, 6/1990.
Guarino, "Measuring Equipment for the Physical Channel of FDDI", SPIE-Int. Soc. Opt. Eng. (U.S.A.), vol. 991, pp. 96-104, 1988.
Mokhoff, "Five-Chip Tokey-Passing Set Operates LANs at 100 Mbits/s", Electronic Design, 9/17/87.
Ullal et al., "Fiber Optic Network Standard Delivers Speed and Reliability", Computer Design, 10/1/87.
McCool, "Implementing FDDI with Supernet (T.M.) Chip Set", Presented at FOC/LAN Conf., 10/29/87.
Annamal et al., "FDDI Chips: The Dawn of a New LAN", Electronic System Design Magazine, 10/87.
Ross, "FDDI-An Overview", Unisys (date unknown).

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