Fault-tolerant waferscale integrated circuit device and method

Details Fault-tolerant waferscale integrated circuit device and method Fault-tolerant waferscale integrated circuit device and method

1993-02-12

1995-07-04

Voeltz, Emanuel T.

Excavating

371221, 371 161, 395800, H04B 1700

Patent

active

054307341

ABSTRACT:
A fault tolerant IC device is made from a wafer of field programmable gate arrays (FGPA's). Each FGPA is first tested and a wafer map of defective FGPA locations is recorded. A hardware description defines desired circuit operation either via a schematic or a functional description such as a equation or a formula. The hardware description is compiled into a list of required wafer resources and a partitioner allocates this list among the resources available in the FGPA's on the wafer. A automatic router then interconnects to implement the circuit function using the wafer map to avoid all defective FGPA locations. A bit-stream generator then generates the configuration data to program each FGPA to perform it's desired function. The resulting wafer-scale circuit is wafer fault tolerant since the programming avoids and non-functional portions of the wafer. Possible embodiments include XILINX FGPAs, custom wafers with FGPAs and special circuitry and wafers having FGPAs programmed to form RISC processors.

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Babb, Tessier and Agarwal, Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators Jan. 26, 1993 pp. 1-15.

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