Fault-tolerant system employing multi-microcomputers using two-o

Details Fault-tolerant system employing multi-microcomputers using two-o Fault-tolerant system employing multi-microcomputers using two-o

1980-09-29

1983-07-05

Zache, Raulfe B.

Boots, shoes, and leggings

371 11, 371 36, G06F 1118

Patent

active

043921990

ABSTRACT:
A Fault-tolerant computer architecture employs a plurality of microcomputers connected in a partially meshed ring. Three device controllers are connected to any of the microcomputers by means of a passive switch, and a fault in data transmission relative to one microcomputer is resolved by a two-out-of-three decision. A failure of one microcomputer is manifested by an adjacent microcomputer, so that the down microcomputer is omitted from furthwr task assignments.

REFERENCES:
patent: 3735356 (1973-05-01), Yates
Wakerly, J. F., "Microcomputer Reliability Improvement Using Triple-Modular Redundancy," Proc. IEEE, vol. 64, No. 6, Jun. 1976, pp. 889-895.

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