Fault tolerant, synchronized twin computer system with error che

Details Fault tolerant, synchronized twin computer system with error che Fault tolerant, synchronized twin computer system with error che

1989-07-19

1993-10-19

Lee, Thomas C.

Excavating

395550, 395575, 371 91, 371 683, 364229, 364265, 364266, 364268, 3642683, 3642689, 364269, 364DIG1, G06F 1116

Patent

active

052553671

ABSTRACT:
A dual processor computer system includes a first processing system having a central processing unit which executes a series of data processing instructions, a data bus system for transferring data to and from the first central processing unit, a memory unit coupled to the first central processing unit, and a cross-link communications element for transferring data into and out of the first processing system. A similarly configured second processing system, operating independently of the first processing system, is also provided. The cross-link communications element associated with the second processing system is coupled to the cross-link communication element of the first processing system, for transferring data into the second processing system from the first processing system and for transferring data into the first processing system from the second computer system.

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