Fault tolerant signal processing machine and method

Details Fault tolerant signal processing machine and method Fault tolerant signal processing machine and method

1988-09-30

1990-10-16

Atkinson, Charles E.

Excavating

371 371, G06F 1110

Patent

active

049641263

ABSTRACT:
The machine includes a plurality of processors each performing identical linear processing operations on its input signal. At least one checksum processor is provided to perform the same linear processing operation as the plurality of processors. Computing apparatus using inexact arithmetic forms a linear combination of the input signals to form an input checksum signal and for operating on the input checksum signal with the checksum processor to generate a processed input checksum signal. The same linear combination of the outputs of the plurality of processors is formed to produce an output checksum signal and the output checksum signal is compared with the processed input checksum signal to produce an error syndrome. A generalized likelihood ratio test is formed from the error syndrome for assessing a likeliest failure hypothesis. The fault tolerant multiprocessor architecture exploits computational redundancy to provide a very high level of fault tolerance with a small amount of hardware redundancy. The architecture uses weighted checksum techniques, and is suited for linear, digital, or analog signal processing.

REFERENCES:
patent: 4517639 (1985-05-01), Ferrell et al.
patent: 4654857 (1987-03-01), Samson et al.
Jou et al., "Fault-Tolerant Matrix Operations on Multiple Processor Systems Using Weighted Checksums", Real Time Signal Processing VII, vol. 495, (1984), pp. 94-101.
Huang et al., "Algorithm-Based Fault Tolerance for Matrix Operations", IEEE Trans on Computers, vol. C-33, No. 6, (1984).
Jou et al., "Fault-Tolerant Matrix Arithmetic and Signal Processing on Highly Concurrent Computing Structures", Proc. IEEE, (1986), pp. 732-741.
Huang et al., "Low Cost Schemes for Fault Tolerance in Matrix Operations with Processor Arrays", Fault-Tolerant Computing, (1982), pp. 330-337.
Chou, "Algorithm-Based Error Detection of a Cholesky Factor Updating Systolic Array Using CORDIC Processors", Real Time Signal Processing XI, vol. 977, (1988), pp. 104-111.
Song et al., "A Fault-Tolerant Architecture for a Parallel Digital Signal Processing Machine", IEEE Int'l Conf. Comp. Design, (1987), pp. 385-390.

Affiliated with

Also associated with

Rating

Fault tolerant signal processing machine and method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fault tolerant signal processing machine and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fault tolerant signal processing machine and method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-855621