Fault tolerant semiconductor system

Details Fault tolerant semiconductor system Fault tolerant semiconductor system

2005-04-05

2005-04-05

Tang, Minh N. (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S763010, C324S1540PB

Reexamination Certificate

active

06876221

ABSTRACT:
A semiconductor system includes a plurality of semiconductor chips, a first group of wirings, a second group of wirings and a connection rearrange wiring section. The first group of wirings interconnect the plurality of semiconductor chips. The second group of wirings are used for redundancy and interconnect the plurality of semiconductor chips. The connection rearrange wiring section includes a connection test circuit and connection rearrange circuit. The connection test circuit makes a test for connection between the plurality of semiconductor chips by means of the first group of wirings. The connection rearrange circuit makes unusable a wiring of the first group in which poor connection occurs and rearranges the connection between the semiconductor chips by use of the wiring of the second group when the poor connection is detected in the wiring of the first group by the connection test circuit.

REFERENCES:
patent: 4288911 (1981-09-01), Ports
patent: 4479088 (1984-10-01), Stopper
patent: 5059899 (1991-10-01), Farnworth et al.
patent: 6002267 (1999-12-01), Malhotra et al.
Ronald P. Cenker, et al. “A Fault-Tolerant 64K Dynamic Random-Access Memory”, IEEE Transactions on Electron Devices, vol. ED-26, No. 6, Jun. 1979, pp. 853-860.

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