Fault tolerant queue system

Details Fault tolerant queue system Fault tolerant queue system

1994-11-14

1997-02-11

Beausoliel, Jr., Robert W.

395427, G06F 1100

Patent

active

056029888

ABSTRACT:
A fault tolerant queue system for buffering data in a packet switch with a common buffer memory for one or more output ports from the switch uses a number of pointers identifying storing positions in the buffer memory. Multiple copies of the same pointer are handled in a controlled way by using a multiple pointer list where the number of copies included in the system of respective pointers are recorded. A maintenance function checks that the number of copies of a pointer agrees with the value recorded in the multiple pointer list for the respective pointer. The maintenance function cyclically checks all pointers and appurtenant buffer positions, one at the time. This is preceded by an initiation procedure during which the pointer is taken out of operation by filtering out the pointer from the flow of pointers which from output queue lists for queueing pointers in queue to the output ports of the memory are returned to the idle list, until the queue system has been emptied of each copy of the pointer in question. Thereupon, the number of returned copies of the pointer in question is compared with the value in the multiple pointer list. The maintenance function can thereafter work in accordance with one or more operating modes for performing the cyclical control.

REFERENCES:
patent: 3863227 (1975-01-01), Sanabria
patent: 4049956 (1977-09-01), Van Veen
patent: 4933932 (1990-06-01), Quinquis et al.
patent: 4953157 (1990-08-01), Franklin et al.
patent: 5014266 (1991-05-01), Bales et al.
patent: 5016248 (1991-05-01), Kudoh
patent: 5291482 (1994-03-01), McHarg et al.
patent: 5388238 (1995-02-01), McHarg et al.
patent: 5432908 (1995-07-01), Heddes et al.
patent: 5485453 (1996-01-01), Wahlman et al.
R. Treuer et al., "Built-In Self-Diagnosis for Repairable Embedded RAMS", IEEE Design & Test of Computers, 1993, pp. 24-33.
C. H. Stapper et al., "Synergistic Fault-Tolerance for Memory Chips", IEEE Transactions on Computers, vol. 41, No. 9, Sep. 1992, pp. 1078-1087.
Ad J. Van De Goor, "Using March Tests to Test SRAMs", IEEE Design & Test of Computers, Mar. 1993, pp. 8-14.
"Technique for Defect Management in Computer Main Memory", IBM Technical Disclosure Bulletin, vol. 35, No. 1A, Jun. 1992, pp. 357-358.

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