Fault-tolerant parallel processing system

Details Fault-tolerant parallel processing system Fault-tolerant parallel processing system

1988-04-28

1990-03-06

Fleming, Michael R.

Excavating

371 113, G06F 1100

Patent

active

049072323

ABSTRACT:
A fault tolerant processing system which includes a plurality of at least (3f+1) fault containment regions each including a plurality of processors and a network element connected to each of the processors and to the network elements of the other regions. Groups of processors are used to form redundant processing sites, the number of each group being included in a different fault containment region. The operations of the network elements are synchronized and the system can be arranged to re-configure the groups of processors so as to form different pluralities of redundant processing sites.

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Roger M. Kieckhafer et al., "The MAFT Architecture for distributed Fault Tolerance," IEEE Transactions on Computers, vol. 37, No. 4, Apr. 1988, pp. 398-405.
Albert L. Hopkins, Jr. et al., "FTMP-A Highly Reliable Fault-Tolerant Multiprocessor for Aircraft", Proceedings of the IEEE, vol. 66, No. 10, Oct. 1978, pp. 1221-1239.
J. H. Lala et al., "A Fault Tolerant Processor to Meet Rigorous Failure Requirements", The Charles Stark Draper Laboratory, Inc.
Daniel L. Palumbo et al., "A Performance Evaluation of the Software-Implemented Fault-Tolerance Computer", J. Guidance, vol. 9, No. 2, Mar.-Apr. 1986, pp. 175-180.

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