Fault-tolerant neighborhood-disjoint address logic for solid...

Details Fault-tolerant neighborhood-disjoint address logic for solid... Fault-tolerant neighborhood-disjoint address logic for solid...

2001-10-13

2003-03-18

Tran, M. (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S200000

Reexamination Certificate

active

06535455

ABSTRACT:

BACKGROUND
The present invention relates to information storage devices. More specifically, the present invention relates to address logic for solid state memory.
Portable devices such as PDAs, handheld computers, digital cameras and digital music players include memory for storing data, digital images and MP3 files. Different types of memory are available for these portable devices. Conventional memory types include flash memory, mini-hard drives, mini-compact discs, and magnetic tape. However, each of these memory types has one or more of the following limitations: large physical size, low storage capacity, relatively high cost, poor robustness, slow access time and high power consumption.
Solid state diode-based OTP memory is disclosed in assignee's U.S. Ser. No. 09/875,356 filed Jun. 5, 2001. Compared to the conventional memory, the diode-based memory has a high shock tolerance, low power consumption, fast access time, moderate transfer rate and good storage capacity. The diode-based memory can fit into a standard portable interface (e.g., PCMCIA, CF) of a portable device.
In a diode-based memory device having multiple levels, each level has main memory and address logic (unlike conventional solid state memory such as DRAM). The address logic of the diode-based memory device is programmable. The address logic may be programmed after each level has been fabricated. Since no masking is required, physical processing is simplified.
Fault-tolerant address logic is desirable. If an address line is unusable, fault-tolerant address logic can still address the main memory.
Neighborhood-disjoint address logic is also desirable for the type of address logic disclosed in assignee's U.S. Ser. No. 09/911,919 filed Jul. 24, 2001. Neighborhood-disjoint address logic allows the memory to be formed at higher resolution.
SUMMARY
According to one aspect of the present invention, a set of address elements is configured by assigning a set of constant weight code words satisfying inequality (2w+t+1)≦n, where w is the weight of the code words, n is the number of address lines, and t is the maximum allowable number of defective address lines.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the present invention.


REFERENCES:
patent: 6466512 (2002-10-01), Hogan et al.

Affiliated with

Also associated with

Rating

Fault-tolerant neighborhood-disjoint address logic for solid... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fault-tolerant neighborhood-disjoint address logic for solid..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fault-tolerant neighborhood-disjoint address logic for solid... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3045972