Fault-tolerant multiprocessor arrangement

Details Fault-tolerant multiprocessor arrangement Fault-tolerant multiprocessor arrangement

1986-12-15

1989-04-04

Atkinson, Charles E.

Excavating

371 12, 364200, G06F 1120

Patent

active

048192325

ABSTRACT:
When a fault is detected in a processor, program execution in this processor is interrupted and taken up again by a standby processor from an earlier uncorrupted state, a recovery point. Such recovery points are specially provided in the program. A save copy of the state at the recovery points is created in each case in a state save unit by recording changes compared with the respective previous state. The data memory existing in the state save unit has pairs of memory words, in which arrangement the state at the recovery point last reached is in each case saved in one of the memory words and the current changes are in each case recorded in the respective other memory word. The memory words are accessed via pointers which are formed by a control logic from two check bits allocated to each memory word pair. Processing of the check bits and of the pointers is very fast. It is not necessary to copy data within the state save unit. The standby processor has direct access to the saved data.

REFERENCES:
patent: 4030074 (1977-06-01), Giorcelli
patent: 4443849 (1984-04-01), Ohwada
patent: 4700292 (1987-10-01), Campanini
patent: 4710926 (1987-12-01), Brown et al.
Wexler, Checkpoint Updating, IBM Technical Disclosure Bulletin, vol. 13, No. 6, Nov. 1970, pp. 1585-1586.
Dieterich et al., A Compatible Airborne Multiprocessor, Proc. of Fall Joint Computer Conf., 18-20, Nov. 1969, Las Vegas, AFIPS Montvale (U.S.A.), pp. 347-357.

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