Fault tolerant memory using bus bit aligned Reed-Solomon error c

Details Fault tolerant memory using bus bit aligned Reed-Solomon error c Fault tolerant memory using bus bit aligned Reed-Solomon error c

1992-05-05

1994-05-17

Beausoliel, Jr., Robert W.

Excavating

371 401, G06F 1110

Patent

active

053134648

ABSTRACT:
A symbol interleaving method for organizing data in a semiconductor memory such that fault tolerance of the memory is optimized when used in conjunction with a Reed-Solomon burst error correcting code. The Reed-Solomon symbols are aligned with respect to the bus bits of the memory such that the impact of a bus bit failure that affects all memory devices in the memory using the bus is constrained within the correction capability of the ECC. The symbols also are distributed among the memory devices in order to maximize fault tolerance. Up to two memory devices in the preferred embodiment may fail without exceeding the correction capability of the code.

REFERENCES:
patent: 4782490 (1988-11-01), Tenengolts
patent: 5099484 (1992-03-01), Smelser
patent: 5134619 (1992-07-01), Henson et la.
patent: 5140592 (1992-08-01), Idleman et al.
patent: 5172379 (1992-12-01), Burrer et al.

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