Fault tolerant memory system which utilizes data from a shadow m

Details Fault tolerant memory system which utilizes data from a shadow m Fault tolerant memory system which utilizes data from a shadow m

1994-12-23

1997-04-08

Beausoliel, Jr., Robert W.

39518505, 39518507, 39518318, G06F 1100

Patent

active

056196423

ABSTRACT:
A fault tolerant memory system is disclosed which includes a main memory device, storing data and an associated error detecting code, and a shadow memory device, storing data corresponding to the data stored in the main memory. A multiplexer, selectively couples data from either the main memory device or the shadow memory device to an output terminal in response to a control signal. A controller reads the data and associated error detecting code from the main memory device and the corresponding data from the shadow memory device, and generates the multiplexer control signal such that the multiplexer couples data from the shadow memory device to the output terminal if the data from the main memory device is not the same as the data from the shadow memory device and the error detecting code indicate an error in the data from the main memory device, and otherwise couples the data from the main memory device to the output terminal.

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