Fault tolerant memory system

Details Fault tolerant memory system Fault tolerant memory system

1992-09-29

1995-01-03

Beausoliel, Jr., Robert W.

Excavating

371 471, 364271, 3642711, G06F 1108

Patent

active

053794150

ABSTRACT:
A memory system in which fault tolerance is achieved utilizing redundant clocks. The redundant clocks are synchronized, and a voter is used to deselect nonmatching clocks, thereby avoiding clocking errors. A circuit is provided to ensure a nonoscillating clock provides an output level at a desired state. Another circuit is provided to ensure oscillation upon power up.

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