Fault tolerant memory system

Details Fault tolerant memory system Fault tolerant memory system

1995-06-06

1996-09-03

Beausoliel, Jr., Robert W.

Excavating

371 36, G01R 3128, G06F 1100

Patent

active

055532314

ABSTRACT:
A fault tolerant clock system is provided by utilizing redundant clocks which are maintained in synchronization, with voting circuit serving to select one of a plurality of matching clock signals for use. A resistor is coupled in series between the crystal and the oscillation circuit in order to establish a desired duty cycle of the clock signal. A series connected diode capacitor network is connected between a node of the oscillator circuit and a power supply in order to ensure initiation of oscillation.

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