Fault-tolerant memory system

Details Fault-tolerant memory system Fault-tolerant memory system

1984-12-03

1987-03-24

Atkinson, Charles E.

Excavating

364900, 365200, 371 11, G11C 800, G11C 2900

Patent

active

046530509

ABSTRACT:
A semiconductor memory structure having multiple memory modules that can be assigned or reassigned to serve in different logical memory locations, to obviate fault conditions detected in one or more modules. A logical addressing scheme treats the memory as having P pages, each with N multibit memory words. The memory modules are each 1.times.N bits in size and each module provides one bit of memory at the same bit position in every word in the page. This minimizes the effect of radiation damage, since a damaged module will affect only one bit in each word, and one missing bit in a word can be reconstructed using conventional error detection and correction techniques. The memory structure includes a memory mapping unit, which yields a set of module assignments for each page of memory.

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