Fault tolerant memory system

Static information storage and retrieval – Addressing – Plural blocks or banks

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Details

36523005, 371 491, 371 511, G11C 800, G06F 1100

Patent

active

059432870

ABSTRACT:
A memory system for storing data comprising a plurality of sets of bits. The system includes a memory section having a pair of ports and a plurality of memory banks. Each one of the memory banks has a plurality of addressable memory units. Each one of the memory units has: memory address control terminal; and data terminals. Each one of the sets of data is fed to the data terminals of a corresponding one of the memory units in each one of the memory banks. The system includes a pair of address control signal driver sections, each one fed by a corresponding one of the pair of ports. A pair of address control signals may be fed to a corresponding one of the pair of ports. A pair of port control logics is coupled a corresponding one of the ports and a corresponding one of the address control signal driver sections. Each one of the port logic sections is adapted to detect a fault in address control signals fed to the port thereof and to report such fault to the source of the first address control signals. The plurality of address control signal driver sections is coupled to a common bus for carrying address control signals to the plurality of driver sections. Each one of the driver sections and each one of the port control logics is adapted to detect a fault in address control signals fed thereto and, if a fault is detected, report such fault to a source of the address control signal, convert the address control signal to a "no operation" command, and transmit such "no operation" command to the memory address control signal terminals of a corresponding one of the addressable memory units in each one of the memory banks.

REFERENCES:
patent: 5577004 (1996-11-01), Leshem
patent: 5612965 (1997-03-01), Michaelson
patent: 5793774 (1998-08-01), Usui et al.

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