Fault-tolerant memory address decoder

Details Fault-tolerant memory address decoder Fault-tolerant memory address decoder

1995-10-23

1998-11-03

Chung, Phung M.

Excavating

365201, 365200, 371 212, G11C 2900

Patent

active

058319867

ABSTRACT:
Hard-open defects between logic gates of an address decoder and the voltage supply render a memory conditionally inoperative. The decoders are therefore examined for such hard-open defects. Two cells of two logically adjacent rows or columns are written with complementary logic data. If a Read operation reveals the data in the two cells to be identical, the presence and location of a hard-open defect in the decoders is demonstrated. Alternatively, the memory is provided with a fault-tolerant decoder that comprises additional disabling circuitry to properly disable the rows and columns even when a hard-open defect is present in the decoders' logic gates.

REFERENCES:
patent: 5357470 (1994-10-01), Namekawa et al.
patent: 5398212 (1995-03-01), Imura et al.
patent: 5436910 (1995-07-01), Takeshima et al.
"A New Testing Acceleration Chip for Low-Cost Memory Tests", by M. Inoue et al, IEEE Design & Test of Computers, Mar. 1993, pp. 15-19.
"Efficient Algorithms for Testing Semiconductor Random Access Memories", by R. Nair et al, IEEE Trans. Computer, vol. C-27, pp. 572-576, Jun. 1978.

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