Fault tolerant memory

Details Fault tolerant memory Fault tolerant memory

1984-09-28

1987-09-08

Fleming, Michael R.

Excavating

371 21, 365201, G06F 1110

Patent

active

046929231

ABSTRACT:
A memory array architecture configured in one form with multiple subarrays addressable by row lines, bank select lines and column select lines, arranged so that no two data word bit positions have a common row line also share common bank select lines. The addition of isolation between the row lines and the row bus combined with the shifting or jogging of the bank select lines in adjacent subarrays ensures that a short circuit or open circuit in a row line no longer effects multiple bits in a common word. The ability to control the effects of manufacturing defects so that they commonly effect no more than a single bit position within a word makes feasible the use of error correction coding techniques within for example integrated circuit ROM type memories.

REFERENCES:
patent: 4335459 (1982-06-01), Miller
patent: 4412314 (1983-10-01), Proebsting
patent: 4542454 (1985-09-01), Breich
patent: 4562576 (1985-12-01), Ratcliffe
patent: 4604749 (1986-08-01), Shinoda
patent: 4617660 (1986-10-01), Sakamoto

Affiliated with

Also associated with

Rating

Fault tolerant memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fault tolerant memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fault tolerant memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2163261