Fault tolerant interconnection networks

Details Fault tolerant interconnection networks Fault tolerant interconnection networks

1989-11-30

1992-07-14

Safourek, Benedict V.

Multiplex communications

Wide area network

Packet switching

370 655, H04J 302

Patent

active

051310414

ABSTRACT:
A multi-stage, alternate routing switching network is enhanced with a switch architecture that is able to detect and mask all single faults. The switch employs a controller that develops dual rail control signals. In one embodiment, the controller is made up of two controllers that receive the same inputs but generate complementary outputs. The complementary outputs form the dual rail signals that control the multiplexers that are interposed between the inputs and the outputs of the switch. The dual rail control of the signal routing within the switch allow for effective detection of all signal faults in the signal routing means. Inclusion of totally self checking circuits at the switch outputs as well as inputs enables users to readily isolate a fault and identify its source.

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Carter and Schneider, "Designs of Dynamically Checked Computers," IFIP68, vol. 2, Edinburg, Scotland, Aug. 1968, pp. 878-883.

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