Fault tolerant hypercube computer system architecture

Details Fault tolerant hypercube computer system architecture Fault tolerant hypercube computer system architecture

1987-10-29

1989-09-19

Smith, Jerry

Excavating

3642294, 3642679, 3649755, 36494067, 36494251, 364944, 3649441, 3649494, 371 91, 371 62, G06F 1120, G06F 1130

Patent

active

048688185

ABSTRACT:
A fault-tolerant multi-processor computer system of the hypercube type comprising a hierarchy of computers of like kind which can be functionally substituted for one another as necessary. Communication between the working nodes is via one communications network while communications between the working nodes and watch dog nodes and load balancing nodes higher in the structure is via another communications network separate from the first. A typical branch of the hierarchy reporting to a master node or host computer (50) comprises, a plurality of first computing nodes (22); a first network of message conducting paths (30) for interconnecting the first computing nodes (22) as a hypercube (28'), the first network (30) providing a path for message transfer between the first computing nodes (22); a first watch dog node (40); and, a second network of message conducting paths (34) for connecting the first computing nodes (22) to the first watch dog node (40) independent from the first network (30), the second network (34) providing an independent path for test message and reconfiguration affecting transfers between the first computing nodes (22) and the first switch watch dog node (40). There is additionally, a plurality of second computing nodes (22); a third network of message conducting paths (30) for interconnecting the second computing nodes (22) as a hypercube (28'), the third network (30) providing a path for message transfer between the second computing nodes (22); a fourth network of message conducting paths (34) for connecting the second computing nodes (22) to the first watch dog node (40) independent from the third network (30) the fourth network (34) providing an independent path for test message and reconfiguration affecting transfers between the second computing nodes (22) and the first watch dog node (40); and, a first multiplexer disposed between the first watch dog node (40) and the second and fourth networks (34) for allowing the first watch dog node (40) to selectively communicate with individual ones of the computing nodes (22) through the second and fourth networks (34); as well as, a second watch dog node (40) operably connected to the first multiplexer whereby the second watch dog node (40) can selectively communicate with individual ones of the computing nodes (22) through the second and fourth networks (34). The branch is completed by a first load balancing node (

REFERENCES:
IEEE Micro, Armstrong et al., "A Fault-tolerant Multimicroprocessor-based Computer System for Space-based Signal Processing", Dec. 1984, pp. 54-65.
Communications of the ACM, Seitz, "The Cosmic Cube", Jan. 1985, vol. 28, No. 1, pp. 22-23.
Proc. 1985 Int'l. Conf. on Parallel Processing, Tuazon et al., "Caltech/JPL Mark II, Hypercube Concurrent Processor", Aug. 1985, pp. 666--673.
Proc. 1985 Int'l. Conf. on Parallel Processing, Peterson et al., "The Mark III Hypercube-Ensemble Concurrent Processor", Aug. 1985, pp. 71-73.
Proc. IEEE, Koren et al., "Yield and Performance Enhancement Through Redundancy in VLSI and WSI Multiprocessor Systems", vol. 74, No. 5, May 1986, pp. 699-711.

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