Fault tolerant gate array using duplication only

Details Fault tolerant gate array using duplication only Fault tolerant gate array using duplication only

1992-06-23

1994-11-29

Beausoliel, Jr., Robert W.

Excavating

371 671, G06F 702, H04L 100

Patent

active

053696549

ABSTRACT:
The FAULT TOLERANT GATE ARRAY USING DUPLICATION ONLY shown here renders AND-drives-OR, and OR-drives-AND, gate arrays as fault tolerant as when triplicated, but does so by only duplicating the array. A test input is added to each of gates of the bottom tier of the two arrays. When a test signal is applied, the same output should be produced by both arrays. This output should be the same as an expected test output, which is known in advance. When the test signal is withdrawn, the two arrays should continue to produce the same output as each other, although it may or may not be the same as the output under test. If any of these three conditions is not met, the failure may be used to determine the correct output, the failed array, and the nature of the failure.

REFERENCES:
patent: 3517174 (1970-01-01), Ossfeldt
patent: 3859513 (1975-01-01), Chuang et al.
patent: 3890493 (1975-06-01), Burtness et al.
patent: 4200225 (1980-04-01), Ueno et al.
patent: 4621201 (1986-11-01), Amdahl et al.
patent: 4713606 (1987-12-01), Laviron
patent: 4903270 (1990-02-01), Johnson et al.

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