Excavating
Patent
1993-03-02
1995-12-05
Beausoliel, Jr., Robert W.
Excavating
371 211, 365222, G06F 1216, G11C 1140
Patent
active
054737702
ABSTRACT:
A fault tolerant computer system having a plurality of processor modules having independent clocks for processing an instruction stream, global memory accessible by all of the processor modules, and a local memory configured within each processor module and clocked synchronously therewith. The local memory is periodically refreshed between accesses to the local memory by the processor. Warning signals indicating a potential access to the local memory are provided to a refresh controller and the local memory is refreshed or the refresh is aborted depending upon the number of clock cycles available before a local memory access occurs. A speculative refresh may be stalled until a processor instruction is decoded to determine whether a local memory access is requested or not.
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Beausoliel, Jr. Robert W.
Fisch Alan M.
Tandem Computers Incorporated
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