Patent
1993-11-04
1996-01-16
Beausoliel, Jr., Robert W.
G06F 1134
Patent
active
054856043
ABSTRACT:
In each module (11) of three or more central processor modules of a fault tolerant computer system, a detector (45) receives a comparator output signal and like comparator output signals from two adjacent modules and produces a detector output signal which confirms absence and presence of a fault in one of the above-mentioned each module. When the fault is confirmed, a controller or processor (49) isolates the module under consideration from the system by inhibiting delivery of a controlled output signal to a bus (31) and by connecting, with the module in question bypassed, switching units (53(1), 53(2)) of the adjacent modules. Preferably, one of the modules of the system is used as a master module of ordinarily delivering the controlled output signal to the bus with others used as checker modules of ordinarily inhibiting the delivery. When a fault appears in the master module, its controller delivers a module operation switching signal to the controllers of the checker modules to thereby substitute one of the checker modules for the master module subjected to the fault.
REFERENCES:
patent: 3681578 (1972-08-01), Stevens
patent: 4750177 (1988-06-01), Hendrie et al.
patent: 4817091 (1989-03-01), Katzman et al.
Hihara Hiroki
Miyoshi Hiroaki
Mizushima Yasuhiko
Ohtsuka Makoto
Beausoliel, Jr. Robert W.
Chung Phung My
NEC Corporation
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