Fault tolerant computer memory systems and components employing

Details Fault tolerant computer memory systems and components employing Fault tolerant computer memory systems and components employing

1995-06-07

1996-07-02

Beausoliel, Jr., Robert W.

Excavating

371 381, 371 391, G06F 1110

Patent

active

055330363

ABSTRACT:
In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which are tied to a system level error correction function, memory reliability is enhanced by providing means for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

REFERENCES:
patent: 4706249 (1987-11-01), Nakagawa et al.
patent: 4706250 (1987-11-01), Patel
patent: 5022031 (1991-06-01), Baggen
patent: 5228046 (1993-07-01), Blake et al.

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